公开(公告)号：US5260227A

公开(公告)日：1993-11-09

申请号：US981032

申请日：1992-11-24

申请人： Joseph E. Farb ,  Kuan Y. Liao ,  Maw-Rong Chin

发明人： Joseph E. Farb ,  Kuan Y. Liao ,  Maw-Rong Chin

IPC分类号： H01L29/80 ,  H01L21/335 ,  H01L21/265

CPC分类号： H01L29/66416

摘要： A method of fabricating self aligned static induction transistors. The method comprises fabricating an N silicon on N.sup.- silicon substrate having an active area. A guard ring is formed around the active area. An N.sup.+ polysilicon layer is formed that comprises source and gate regions. An oxide layer is formed on the N.sup.+ polysilicon layer. A second polysilicon layer is formed on the oxide layer. A second oxide layer is formed on the second polysilicon layer which is then masked by a self aligning mask. Trenches are etched into the substrate using the self aligning mask and gate regions are formed at the bottom of the trenches. A first layer of metal (gate metal) is deposited to make contact with the gate regions. A layer of photoresist is deposited and planarized, and the first layer of metal is overetched below the top surface of the trench. Plasma nitride is deposited and planarized, and a polysilicon mask is deposited over the planarized layer of plasma nitride. The polysilicon mask is etched to expose the gate metal disposed on the field. A second layer of metal is deposited to make contact with the source and gate regions. A passivation layer is formed, and interconnection pads are formed that connect the first and second layers of metal. The present method employs a single minimum geometry trench mask. The key features of the transistor are defined by the trench mask and related processing parameters. Because of the self alignment achieved by the present invention, the number of channels per unit area is higher, which results in higher transconductance. In addition, some of the parasitic capacitance is eliminated by the present invention, resulting in faster operational speed. The variable sidewall trench oxide thickness allows fabrication of static induction transistors with higher or lower breakdown voltages according to the thickness that is chosen, and for a more graded P gate junction.

公开(公告)号：US4920403A

公开(公告)日：1990-04-24

申请号：US338682

申请日：1989-04-17

申请人： Yu C. Chow ,  Kuan Y. Liao ,  Maw-Rong Chin ,  Charles S. Rhoades

发明人： Yu C. Chow ,  Kuan Y. Liao ,  Maw-Rong Chin ,  Charles S. Rhoades

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L23/52

CPC分类号： H01L21/7684 ,  H01L21/76886

摘要： Methods of fabricating metal interconnection lines in an integrated circuit. In general, one method comprises the steps of depositing a layer of metal on an inter-dielectric oxide layer. The layer of metal is patterned and etched to form metal interconnection lines over the oxide layer. Tungsten is selectively deposited onto the etched layer to completely form the metal interconnection lines. Additionally, in a second method, a layer of tungsten may be deposited prior to the layer of metal. This forms a metal line that is completely encapsulated in tungsten. In addition, selective tungsten employed to repair broken metal lines in a fabricated integrated circuit. The selective tungsten is deposited using a chemical vapor deposition process and is deposited onto masked and etched second level (or higher) metal lines formed in the integrated circuit. The method of selectively depositing tungsten comprises the steps of exposing the metal interconnection lines to a mixture of SiH.sub.4 at a rate between 3-10 standard cubic centimeters per minute, WF.sub.6 at a rate between 3-25 standard cubic centimeters per minute, and H.sub.2 at a rate between 25-100 standard cubic centimeters per minute. Then the exposed metal interconnection lines are processed at a pressure between 50-200 m Torr, a temperature between 250-350 degrees Celsius, and a deposition rate between 2000-10000 Angstroms per minute to form the fully interconnected metal lines. The present method improves the yields of multi-level metal integrated circuits and maximizes the potential gate usage therein. The conformal deposition of selective tungsten enhances the yields of integrated circuits and tungsten capping on aluminum metal lines, for example provides for a better electromigration resistance interconnection.

摘要翻译： 在集成电路中制造金属互连线的方法。 通常，一种方法包括以下步骤：在介电间氧化物层上沉积金属层。 金属层被图案化和蚀刻以在氧化物层上形成金属互连线。 选择性地将钨沉积到蚀刻层上以完全形成金属互连线。 另外，在第二种方法中，钨层可以在金属层之前沉积。 这形成完全封装在钨中的金属线。 此外，在制造的集成电路中用于修复断裂的金属线路的选择性钨。 使用化学气相沉积工艺沉积选择性钨，并沉积到形成在集成电路中的被掩蔽和蚀刻的第二层（或更高）金属线上。 选择性沉积钨的方法包括以3到10标准立方厘米/分钟的速率将金属互连线暴露于SiH 4的混合物，以3-25标准立方厘米/分钟的速率暴露于金属互连线和H2 一个25-100标准立方厘米每分钟的速率。 然后暴露的金属互连线在50-200m乇，250-350摄氏度的温度和2000-10000埃每分钟的沉积速率之间的压力下进行处理，以形成完全互连的金属线。 本方法提高了多级金属集成电路的产量，并使其中的栅极使用最大化。 选择性钨的共形沉积增强了集成电路的产量和铝金属线上的钨封盖，例如提供了更好的电迁移电阻互连。

公开(公告)号：US4961822A

公开(公告)日：1990-10-09

申请号：US338681

申请日：1989-04-17

申请人： Kuan Y. Liao ,  Yu C. Chow ,  Maw-Rong Chin ,  Charles S. Rhoades

发明人： Kuan Y. Liao ,  Yu C. Chow ,  Maw-Rong Chin ,  Charles S. Rhoades

IPC分类号： H01L21/3205 ,  H01L21/768

CPC分类号： H01L21/76879 ,  H01L21/32051 ,  Y10S257/90

摘要： A method of fabricating higher-order metal interconnection layers in a multi-level metal semiconductor device. The semiconductor device has at least one metal layer, an oxide layer disposed on the metal layer, and a metal plug disposed in the oxide layer connected to the metal layer. A reverse photoresist mask is formed on the oxide layer that is etched to form trenches therein that define the higher-order metal layer. An adhesion layer that comprises titanium tungsten or aluminum is deposited on top of the photoresist mask that contacts the metal plug. A low viscosity photoresist layer is then deposited on top of the adhesion layer. The adhesion layer and low viscosity photoresist layer are then anisotropically etched, and the low viscosity photoresist layer is then removed to expose the adhesion layer. Finally, selective metal, such as tungsten or molybdenum, for example, is deposited on top of the adhesion layer in the trench to form the higher-order metal interconnection layer. Subsequent metal levels may be fabricated by repeating the method starting with the steps of depositing the oxide over the formed higher-order metal lines and forming the metal plugs in the oxide layer.

摘要翻译： 一种在多级金属半导体器件中制造高阶金属互连层的方法。 半导体器件具有至少一个金属层，设置在金属层上的氧化物层和设置在连接到金属层的氧化物层中的金属插塞。 在氧化物层上形成反向光刻胶掩模，该掩模蚀刻以形成限定高级金属层的沟槽。 包含钛钨或铝的粘合层沉积在与金属塞接触的光致抗蚀剂掩模的顶部上。 然后将低粘度的光致抗蚀剂层沉积在粘附层的顶部。 然后对粘合层和低粘度的光致抗蚀剂层进行各向异性蚀刻，然后除去低粘度的光致抗蚀剂层以暴露粘附层。 最后，诸如钨或钼的选择性金属例如沉积在沟槽中的粘附层的顶部上以形成高级金属互连层。 随后的金属水平可以通过以下步骤制造：从在所形成的高级金属线上沉积氧化物并在氧化物层中形成金属塞的步骤开始。

公开(公告)号：US5028564A

公开(公告)日：1991-07-02

申请号：US352583

申请日：1989-04-27

申请人： Chen-Chi P. Chang ,  Kuan Y. Liao ,  Joseph E. Farb

发明人： Chen-Chi P. Chang ,  Kuan Y. Liao ,  Joseph E. Farb

IPC分类号： H01L21/205 ,  H01L21/225 ,  H01L21/8238 ,  H01L21/86 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/86 ,  H01L21/2255 ,  Y10S148/031 ,  Y10S148/044

摘要： Methods of fabricating heavily doped edges of mesa structures in silicon-on-sapphire and silicon-on-insulator semiconductor devices. The methods are self-aligning and require a minimum of masking steps to achieve. The disclosed methods reduce edge leakage and resolve N-channel threshold voltage instability problems. Mesa structures are formed that comprise N-channel and P-channel regions having a thermal oxide layer deposited thereover. A doping layer of borosilicate glass, or alternatively, an undoped oxide layer that is subsequently implanted, is deposited over the mesa structures. In the first method, the doping layer is etched by means of an anisotropic plasma etching procedure to form oxide spacers at the edges of the mesa structures. The doping layer is removed from the N-mesa structures using an N-channel mask and wet oxide etching procedure. The structure is then heated to a relatively high temperature to drive the dopant into the edges of the N-channel mesa structures. The protective layers are then removed by a wet etching procedure. The semiconductor device is fabricated to completion in a conventional manner thereafter. In the second method, a nitride layer is deposited over the mesa structures and thermal oxide layer. A thin oxide layer, which is generally deposited by means of a chemical vapor deposition procedure, is deposited over the silicon nitride layer. The formed structure is then processed to expose the N-channel mesa structures. This is accomplished using an N-well mask, the oxide layer is etched to expose the silicon nitride layer over the N-channel, and the nitride layer covering the N-channel is removed by means of hot phosphoric acid using the oxide layer as a mask. The doping layer is then deposited over the mesa structures. This doping layer is then heated to drive the dopant/implant into the edges of the N-channel mesa structures. The doping layer is then removed by wet oxide etching, the nitride layer is removed by rinsing in hot phosphoric acid and the thermal oxide layer is removed by a wet oxide etching procedure. The semiconductor device is again fabricated to completion in a conventional manner thereafter.

公开(公告)号：US4645562A

公开(公告)日：1987-02-24

申请号：US728012

申请日：1985-04-29

申请人： Kuan Y. Liao ,  Kuang-Yeh Chang ,  Hsing-Chien Ma

发明人： Kuan Y. Liao ,  Kuang-Yeh Chang ,  Hsing-Chien Ma

IPC分类号： H01L21/302 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  B44C1/22 ,  B29C17/08 ,  C03C15/00 ,  C03C25/06

CPC分类号： H01L21/32137 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136

摘要： A photolithographic process useful for VLSI fabrication is disclosed for achieving side-wall profile control of poly lines, metal lines, contact and via openings. Layers of a first and second photoresist materials are formed on the poly, metal or oxide-covered substrate. The top layer is patterned by conventional processes to define the final device geometry. The bottom layer is exposed and over-developed to form an overhang structure about the line pattern or the contact/via opening. During the subsequent anisotropic plasma-assisted etching step, some ions or particles are passed obliquely over the overhang and bombard the opening corner, the side-wall and the under-cut area. The plasma-assisted etching step not only forms the poly or metal lines, or the contact or via opening, but also results in an opening with rounded corners and a smoothly tapered side-wall profile. The subsequent metal film deposition step results in a uniform film thickness around the edges of the opening. The process thus alleviates the problem of high contact resistance previously encountered as a result of dry etching the contact or via openings.

摘要翻译： 公开了一种用于VLSI制造的光刻工艺，用于实现多线，金属线，接触和通孔的侧壁轮廓控制。 第一和第二光致抗蚀剂材料的层在多金属或氧化物覆盖的基底上形成。 通过常规方法对顶层进行图案化以定义最终的装置几何形状。 底层暴露并过度显影以形成围绕线图案或接触/通孔开口的悬垂结构。 在随后的各向异性等离子体辅助蚀刻步骤中，一些离子或颗粒倾斜地穿过悬垂物并且轰击开口角，侧壁和下切区域。 等离子体辅助蚀刻步骤不仅形成多个或金属线，或接触或通孔，而且还形成具有圆角和平滑锥形侧壁轮廓的开口。 随后的金属膜沉积步骤导致围绕开口边缘的均匀的膜厚度。 因此，该方法减轻了由于干蚀刻接触或通孔的结果而先前遇到的高接触电阻的问题。

公开(公告)号：US4767721A

公开(公告)日：1988-08-30

申请号：US827140

申请日：1986-02-10

申请人： Kuan Y. Liao ,  William W. Y. Lee

发明人： Kuan Y. Liao ,  William W. Y. Lee

IPC分类号： H01L21/265 ,  H01L21/027 ,  H01L21/266 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/308

CPC分类号： H01L21/266 ,  H01L21/0272 ,  H01L21/823892 ,  H01L27/0928 ,  Y10S438/951

摘要： A technique is disclosed for obtaining a self-aligned twin-well structure in a CMOS process. A double layer of two different photoresist materials is employed to obtain an overhang photoresist structure used for the p-well masking and ion implantation process. After the p-well implantation, pure aluminum is deposited over the wafer, forming a first layer over the p-well region and a second layer over the photoresist layers. A metal lift-off procedure is performed to dissolve the photoresist layers and thereby remove the second layer of metal. The first layer of aluminum remaining on the wafer forms a conjugate of the p-well pattern and serves as the n-well mask for ion implantation. The invention provides a straightforward method for achieving the self-aligned twin-well structure in CMOS processes, and is adapted to high energy ion implantation for achieving retrograde impurity profiles.

摘要翻译： 公开了一种用于在CMOS工艺中获得自对准双阱结构的技术。 使用双层两种不同的光致抗蚀剂材料来获得用于p阱掩模和离子注入工艺的悬垂光致抗蚀剂结构。 在p阱注入之后，在晶片上沉积纯铝，在p阱区上形成第一层，在光致抗蚀剂层上形成第二层。 执行金属剥离程序以溶解光致抗蚀剂层，从而去除第二层金属。 残留在晶片上的第一层铝形成p阱图案的共轭，并用作离子注入的n阱掩模。 本发明提供了一种用于在CMOS工艺中实现自对准双阱结构的直接方法，并且适用于实现逆向杂质分布的高能离子注入。