公开(公告)号：US4780750A

公开(公告)日：1988-10-25

申请号：US815869

申请日：1986-01-03

申请人： Joseph G. Nolan ,  Michael A. Van Buskirk ,  Te-Long Chiu ,  Ying K. Shum

发明人： Joseph G. Nolan ,  Michael A. Van Buskirk ,  Te-Long Chiu ,  Ying K. Shum

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

CPC分类号： H01L29/7883

摘要： In this invention, an Electrically Alterable Non-Volatile Memory (EANOM) cell is disclosed. The EANOM ceil comprises an MOS transistor, having a source, a gate and a drain. The EANOM cell also has a two-terminal tunnel device, one end of which is connected to the gate of the MOS transistor. The other terminal being labelled "T". The tunnel device causes charges to be stored or removed from the gate of the MOS transistor. In a preferred embodiment, a four-terminal EANOM cell is disclosed. The four terminals of the EANOM cell are terminals T, S (source of the MOS transistor), D (drain of the MOS transistor) and a terminal C which is capacitively coupled to the gate of the MOS transistor. The EANOM cell can be used in a memory circuit to increase the reliability thereof. Two or more EANOM cells are connected in tandem and operate simultaneously. Catastrophic failure of one EANOM cell results in an open circuit with the other EANOM cell continuing to function.

摘要翻译： 在本发明中，公开了电可变非易失性存储器（EANOM）单元。 EANOM ceil包括具有源极，栅极和漏极的MOS晶体管。 EANOM单元还具有两端隧道器件，其一端连接到MOS晶体管的栅极。 另一个终端标记为“T”。 隧道装置使电荷从MOS晶体管的栅极存储或去除。 在优选实施例中，公开了四端子EANOM单元。 EANOM单元的四个端子是端子T，S（MOS晶体管的源极），D（MOS晶体管的漏极）和与MOS晶体管的栅极电容耦合的端子C. EANOM单元可用于存储器电路中以提高其可靠性。 两个或多个EANOM单元串联连接并同时操作。 一个EANOM细胞的灾难性故障导致另一个EANOM细胞继续发挥功能的开路。

公开(公告)号：US5058529A

公开(公告)日：1991-10-22

申请号：US500566

申请日：1990-03-28

申请人： Te-Long Chiu

发明人： Te-Long Chiu

IPC分类号： A01K63/04

CPC分类号： A01K63/047

摘要： The present invention relates to an air-water switching unit which consists of an air-water switching chamber with a movable piston residing inside the chamber and separating air coming into the chamber through an air inlet at one side and water coming into the chamber through a water inlet at the other side of the chamber. An air-water outlet is located between the air inlet and the water inlet. The movement of the piston is controlled by the pressure difference between the air pressure on one side and the water pressure on the other side of the piston. The air mixing water pump according to the present invention comprises the air-water switching unit, an air pump connected to the air inlet of the air-water switching chamber of the air-water switching unit, water supply from the output of a water filter connected to the water inlet of the air-water switching chamber, and a PVC tube connected to the air-water outlet of the air-water switching chamber. The PVC tube goes back to the aquarium at the location above the water level. The present invention also includes the application of the air-water switching unit and the air mixing water pump system in a fountain aquarium and an aquagarden.

摘要翻译： 本发明涉及一种空气 - 水切换装置，该装置包括一个空气 - 水切换室和一个位于室内的活动活塞，并且通过一侧的空气入口分离进入该室的空气，以及通过一个进入该室的水 在室的另一侧的进水口。 空气出口位于进气口和进水口之间。 活塞的运动由一侧的空气压力与活塞另一侧的水压之间的压力差来控制。 根据本发明的空气混合水泵包括空气 - 水切换单元，连接到空气 - 水切换单元的空气 - 水切换室的进气口的空气泵，从水过滤器的输出供水 连接到空气 - 水切换室的进水口，以及连接到空气 - 水切换室的空气出口的PVC管。 PVC管可以返回到水位上方的水族箱。 本发明还包括将空气 - 水切换单元和空气混合水泵系统应用于喷泉水族箱和水槽中。

公开(公告)号：US06359305B1

公开(公告)日：2002-03-19

申请号：US09470212

申请日：1999-12-22

申请人： Te-Long Chiu

发明人： Te-Long Chiu

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

摘要： An EEPROM floating gate memory device includes: a floating gate disposed over the channel between the buried drain and the buried source, and insulated from the channel by 200 Å to 1000 Å of gate oxide; an add-on floating gate shorted electrically to the floating gate, and disposed over and insulated from the buried drain by 15 Å to 150 Å of tunnel dielectric; and a control gate disposed over and insulated from the floating gate and the channel between the floating gate and the buried source. Both the floating gate and the channel underneath are self-aligned to and flanked by the field oxide in the trench along the direction perpendicular to the channel current flow. The add-on floating gate forms both a self-aligned endcap on the field oxide and the self-aligned tunnel area on the buried drain. The architecture allows a reduction in memory cell size. The memory cells are particularly suited for a proposed segmented bit line page memory array architecture with the common drain line and the common source line in separate Y-column direction, and with the common control gate line in the X-row direction. A semiconductor device has a gate disposed over the channel and insulated from the channel by the gate oxide, an add-on poly spacer shorted electrically to the gate, and disposed over and insulated from the lightly doped source and drain by oxide. The add-on poly spacer also foams the self-aligned encap of the device on the field oxide.

摘要翻译： EEPROM浮动栅极存储器件包括：浮置栅极，设置在漏极和掩埋源之间的沟道上方，并且与沟道隔离200埃至1000埃的栅极氧化物; 一个附加的浮动栅极与浮动栅极电连接，并且通过隧道介电层设置在绝缘漏极上并与绝缘绝缘绝缘15Å至150Å; 以及设置在所述浮动栅极和所述浮动栅极与所述掩埋源之间的所述沟槽之上并与之绝缘的控制栅极。 浮动栅极和下面的沟道都沿着垂直于沟道电流的方向在沟槽中自对准并侧接于沟槽中的场氧化物。 附加浮置栅极在场氧化物上形成自对准端帽和埋入漏极上的自对准隧道区域。 该架构允许减少内存单元大小。 存储单元特别适用于分离的位线存储阵列结构，其中共同漏极线和公共源极线分开在Y列方向上，并且公共控制栅极线在X行方向上。 半导体器件具有设置在沟道上方的栅极并且通过栅极氧化物与沟道绝缘，附加的多晶硅衬垫电连接到栅极，并且通过氧化物设置在轻掺杂源极和漏极之上并与其绝缘。 附加聚合物间隔物还将该装置的自对准封装的氧化物发泡在场氧化物上。

公开(公告)号：US5019879A

公开(公告)日：1991-05-28

申请号：US493750

申请日：1990-03-15

申请人： Te-Long Chiu

发明人： Te-Long Chiu

IPC分类号： H01L21/28 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11519 ,  H01L21/2815 ,  H01L27/115 ,  H01L29/7885

摘要： The flash EEPROM memory device with the floating gate that is over the channel area and insulated from the channel by 200 to 1000 A of gate oxide, and that is also over the thin tunnel dielectric area at the source and insulated from the source by 70 A to 200 A of tunnel dielectric. Another improvement of the proposed version of the flash EEPROM memory device is that the tunnel dielectric area is small and self aligned to the floating gate.

摘要翻译： 闪存EEPROM存储器件，其浮动栅极位于通道区域上方并与通道隔离200至1000A的栅极氧化物，并且还在源极处的薄隧道电介质区域并与源极绝缘70 A 到200A的隧道电介质。 闪存EEPROM存储器件的提出版本的另一改进是隧道介电区域小并且与浮置栅极自对准。

公开(公告)号：US5021848A

公开(公告)日：1991-06-04

申请号：US492113

申请日：1990-03-13

申请人： Te-Long Chiu

发明人： Te-Long Chiu

IPC分类号： H01L27/115

CPC分类号： H01L27/115

摘要： The EEPROM has the selection device in series with the memory device having a floating gate disposed over the channel between the buried drain and the buried source, and insulated from the channel by 200 A to 1000 A of gate oxide, an add-on floating gate shorted electrically to the floating gate, and disposed over and insulated from the buried drain by 40 A to 150 A of tunnel dielectric, and a control gate disposed over and insulated from the floating gate. The improvement in the proposed version of the memory device in the EEPROM is that the tunnel dielectric area is very small and is self aligned to the floating gate.

摘要翻译： EEPROM具有与存储器件串联的选择器件，该存储器件具有布置在掩埋漏极和掩埋源之间的沟道上的浮置栅极，并且与沟道绝缘200至1000A的栅极氧化物，附加浮动栅极 与浮动栅极电气短路，并且通过40A至150A的隧道电介质设置在绝缘漏极上并与绝缘绝缘绝缘，以及设置在浮动栅极上并与浮动栅极绝缘的控制栅极。 EEPROM中存储器件的建议版本的改进是隧道介电区域非常小并且与浮动栅极自对准。

公开(公告)号：US4376947A

公开(公告)日：1983-03-15

申请号：US72504

申请日：1979-09-04

申请人： Te-Long Chiu ,  Jih-Chang Lien

发明人： Te-Long Chiu ,  Jih-Chang Lien

IPC分类号： H01L27/112 ,  G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/08 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  G11C11/40

CPC分类号： H01L29/7885 ,  G11C16/0416 ,  H01L29/0847

摘要： An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.

公开(公告)号：US4302766A

公开(公告)日：1981-11-24

申请号：US1097

申请日：1979-01-05

申请人： Daniel C. Guterman ,  Te-Long Chiu

发明人： Daniel C. Guterman ,  Te-Long Chiu

IPC分类号： G11C16/04 ,  H01L29/788 ,  H01L27/02 ,  B01J17/00

CPC分类号： H01L29/7885 ,  G11C16/0433

摘要： A non-volatile semiconductor memory device of the electrically erasable type employs a floating gate which is programmed by application to high voltage across the source and drain so that hot electrons traverse the gate oxide. The floating gate is discharged by electron tunneling through an erase window which is separated from the control gate. Very small cell size is provided by a triple level polysilicon structure.

摘要翻译： 电可擦除型的非易失性半导体存储器件采用浮置栅极，其通过在源极和漏极上施加高电压来编程，使得热电子穿过栅极氧化物。 浮动栅极通过电子隧道通过与控制栅极分离的擦除窗口放电。 非常小的单元尺寸由三重多晶硅结构提供。

公开(公告)号：US4467453A

公开(公告)日：1984-08-21

申请号：US470122

申请日：1983-02-28

申请人： Te-Long Chiu ,  Jih-Chang Lien

发明人： Te-Long Chiu ,  Jih-Chang Lien

IPC分类号： G11C16/04 ,  H01L29/08 ,  H01L29/788 ,  G11C11/40

CPC分类号： H01L29/0847 ,  G11C16/0416 ,  H01L29/7885

摘要： An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.

摘要翻译： N沟道双层多MOS只读存储器或ROM阵列可通过位于由行地址线形成的控制栅极下方的浮动门电可编程。 可以通过将选择的电压施加到源极，漏极，控制栅极和衬底来对电池进行电气编程; 浮动栅极通过浮动栅极和沟道之间的绝缘体充电。 用于制造器件的简化过程消除了光致抗蚀剂和植入步骤，但是以较高增益和较低的身体效应的形式产生改进的特性。

公开(公告)号：US4370798A

公开(公告)日：1983-02-01

申请号：US284846

申请日：1981-07-20

申请人： Jih-Chang Lien ,  Te-Long Chiu

发明人： Jih-Chang Lien ,  Te-Long Chiu

IPC分类号： H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L23/532 ,  H01L27/06 ,  H01L27/11 ,  H01L29/04 ,  H01L29/78

CPC分类号： H01L28/20 ,  H01L21/32105 ,  H01L21/768 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/1112 ,  H01L2924/0002

摘要： Integrated circuit resistor elements ideally suited for load devices in static MOS RAM cells are made in second-level polycrystalline silicon by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The second-level polysilicon is insulated from first-level polysilicon by multi-layer insulation; first, a thermal oxide layer provides better edge breakdown characteristics for transistors, then secondly a layer of doped deposited oxide provides improved step coverage, and finally an undoped deposited oxide is used to prevent out diffusion from doped oxide to second level polysilicon which would change the characteristics of the resistors.

摘要翻译： 集成电路电阻元件理想地适用于静态MOS RAM单元中的负载器件，通过与自对准N沟道硅栅极工艺兼容的离子注入步骤在二级多晶硅中制成。 二级多晶硅通过多层绝缘与一级多晶硅绝缘; 首先，热氧化物层为晶体管提供更好的边缘击穿特性，其次是掺杂沉积氧化物层提供改进的台阶覆盖，最后使用未掺杂的沉积氧化物来防止从掺杂氧化物扩散到第二级多晶硅，这将改变 电阻的特性。

公开(公告)号：US4291328A

公开(公告)日：1981-09-22

申请号：US48961

申请日：1979-06-15

申请人： Jih-Chang Lien ,  Te-Long Chiu

发明人： Jih-Chang Lien ,  Te-Long Chiu

IPC分类号： H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L23/532 ,  H01L27/06 ,  H01L27/11 ,  H01L29/04 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L28/20 ,  H01L21/32105 ,  H01L21/768 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/1112 ,  H01L2924/0002

摘要： Integrated circuit resistor elements ideally suited for load devices in static MOS RAM cells are made in second-level polycrystalline silicon by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The second-level polysilicon is insulated from first-level polysilicon by multi-layer insulation; first, a thermal oxide layer provides better edge breakdown characteristics for transistors, then secondly a layer of doped deposited oxide provides improved step coverage, and finally an undoped deposited oxide is used to prevent out diffusion from doped oxide to second level polysilicon which would change the characteristics of the resistors.

摘要翻译： 集成电路电阻元件理想地适用于静态MOS RAM单元中的负载器件，通过与自对准N沟道硅栅极工艺兼容的离子注入步骤在二级多晶硅中制成。 二级多晶硅通过多层绝缘与一级多晶硅隔离; 首先，热氧化物层为晶体管提供更好的边缘击穿特性，其次是掺杂沉积氧化物层提供改进的台阶覆盖，最后使用未掺杂的沉积氧化物来防止从掺杂氧化物扩散到第二级多晶硅，这将改变 电阻的特性。