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公开(公告)号：US07659740B2
公开(公告)日：2010-02-09
申请号：US12189226
申请日：2008-08-11
申请人： Joseph O. Marsh , Jeremy Stephens , Charlie C. Hwang , James S. Mason , Huihao Xu , Matthew B. Baecher , Thomas J. Bardsley , Mark R. Taylor
发明人： Joseph O. Marsh , Jeremy Stephens , Charlie C. Hwang , James S. Mason , Huihao Xu , Matthew B. Baecher , Thomas J. Bardsley , Mark R. Taylor
CPC分类号： G01R31/3167 , G01R31/318544
摘要： Digital testing of an analog driver circuit is enabled using a circuit including a control circuit for generating signals, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit, and a differential receiver circuit for converting the differential output signal to a single ended signal and transmitting the single ended signal. The testing includes skewing a differential output termination impedance, adjusting a differential receiver circuit voltage offset, selecting a differential driver circuit power level, enabling a decoder which activates only one differential driver circuit segment per test sequence, activating a segment, stimulating the differential driver circuit with digital test patterns, receiving differential driver circuit output, converting the output to a single-ended signal, and observing the single-ended signal.
摘要翻译： 使用包括用于产生信号的控制电路的电路，用于接收差分输入信号的差分驱动器电路，放大差分输入信号和发送差分输出信号来实现模拟驱动器电路的数字测试，用于产生可编程终端阻抗电路 在差分驱动电路的输出节点处的差分终端阻抗，以及用于将差分输出信号转换为单端信号并发送单端信号的差分接收电路。 测试包括偏移差分输出终端阻抗，调整差分接收器电路电压偏移，选择差分驱动器电路功率电平，使得能够在每个测试序列仅激活一个差分驱动器电路段的解码器，激活段，激励差分驱动器电路 具有数字测试模式，接收差分驱动电路输出，将输出转换为单端信号，并观察单端信号。
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公开(公告)号：US20090027075A1
公开(公告)日：2009-01-29
申请号：US12189226
申请日：2008-08-11
申请人： Joseph O. Marsh , Jeremy Stephens , Charlie C. Hwang , James S. Mason , Huihao Xu , Matthew B. Baecher , Thomas J. Bardsley , Mark R. Taylor
发明人： Joseph O. Marsh , Jeremy Stephens , Charlie C. Hwang , James S. Mason , Huihao Xu , Matthew B. Baecher , Thomas J. Bardsley , Mark R. Taylor
IPC分类号： G01R31/28
CPC分类号： G01R31/3167 , G01R31/318544
摘要： A circuit and method of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention comprises a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal. The method of the present invention comprises digitally testing the differential driver circuit by activating a test enable signal, skewing the differential output termination impedance in response to the test enable signal, adjusting a voltage offset of the differential receiver circuit in response to the test enable signal, selecting a power level for the differential driver circuit in response to the test enable signal, enabling a decoder in response to the test enable signal, wherein the decoder activates only one segment of the differential driver circuit during any one test sequence, activating one of the segments for testing, stimulating the differential driver circuit with digital test patterns, receiving an output of the differential driver circuit by the differential receiver circuit, converting the received differential driver output to a single-ended signal, observing the single-ended signal; and deactivating the test enable signal.
摘要翻译： 使用基于数字扫描的测试方法测试模拟驱动器电路的电路和方法。 本发明的电路包括用于响应于测试使能信号产生信号的控制电路，用于接收差分输入信号的差分驱动器电路，放大差分输入信号并响应差分输入信号发送差分输出信号 以及由所述控制电路产生的信号，用于响应于由所述控制电路产生的信号而在所述差分驱动器电路的输出节点处产生差分终端阻抗的可编程终端阻抗电路以及用于从所述差分接收电路接收所述差分输出的差分接收电路 差分驱动器电路将差分输出信号转换为单端信号并传输单端信号，全部是响应于测试使能信号。 本发明的方法包括通过激活测试使能信号来数字测试差分驱动器电路，响应于测试使能信号偏移差动输出终端阻抗，响应于测试使能信号调整差分接收器电路的电压偏移 ，响应于所述测试使能信号选择所述差分驱动器电路的功率电平，使能够响应于所述测试使能信号的解码器，其中所述解码器在任何一个测试序列期间仅激活所述差分驱动器电路的一个部分， 用于测试的段，用数字测试图案刺激差分驱动器电路，通过差分接收器电路接收差分驱动器电路的输出，将接收到的差分驱动器输出转换为单端信号，观察单端信号; 并禁用测试使能信号。
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公开(公告)号：US07466156B2
公开(公告)日：2008-12-16
申请号：US10708788
申请日：2004-03-25
申请人： Joseph O. Marsh , Jeremy Stephens , Charlie C. Hwang , James S. Mason , Huihao Xu , Matthew B. Baecher , Thomas J. Bardsley , Mark R. Taylor
发明人： Joseph O. Marsh , Jeremy Stephens , Charlie C. Hwang , James S. Mason , Huihao Xu , Matthew B. Baecher , Thomas J. Bardsley , Mark R. Taylor
IPC分类号： G01R31/02
CPC分类号： G01R31/3167 , G01R31/318544
摘要： A circuit of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention includes a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal.
摘要翻译： 使用基于数字扫描的测试方法测试模拟驱动器电路的电路。 本发明的电路包括用于响应于测试使能信号产生信号的控制电路，用于接收差分输入信号的差分驱动器电路，放大差分输入信号并响应差分输入信号发送差分输出信号 以及由所述控制电路产生的信号，用于响应于由所述控制电路产生的信号而在所述差分驱动器电路的输出节点处产生差分终端阻抗的可编程终端阻抗电路以及用于从所述差分接收电路接收所述差分输出的差分接收电路 差分驱动器电路将差分输出信号转换为单端信号并传输单端信号，全部是响应于测试使能信号。
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4.发明授权Method and apparatus for generating synchronization signals for synchronizing multiple chips in a system 失效用于产生用于同步系统中的多个芯片的同步信号的方法和装置公开(公告)号：US07826579B2
公开(公告)日：2010-11-02
申请号：US11363871
申请日：2006-02-28
IPC分类号： H04L7/00
摘要： A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically. This invention resolves the uncertainty problem and allows the synchronization signals to be generated deterministically independent of the chip global clock cycle time.
摘要翻译： 一种用于产生多芯片系统的同步信号的时钟发生器电路。 时钟发生器电路包括从参考时钟和具有边缘检测逻辑的芯片全局时钟产生同步信号。 在具有多个芯片的高性能服务器系统设计中，服务器系统的常见做法是使用反馈时钟和延迟参考时钟来生成同步信号。 所产生的同步信号被传送到由全局时钟计时的锁存器，以用于芯片同步功能。 随着系统时钟频率被推高，由反馈时钟所产生的所生成的同步信号与由全局时钟计时的接收锁存器之间的相位差成为这个信号不能被确定地传送的循环时间的大部分。 本发明解决了不确定性问题，并允许确定地产生同步信号，而不依赖于芯片全局时钟周期时间。
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5.发明授权Methods and systems for locally generating non-integral divided clocks with centralized state machines 失效用集中式状态机本地生成非积分分时钟的方法和系统公开(公告)号：US07368958B2
公开(公告)日：2008-05-06
申请号：US11419224
申请日：2006-05-19
IPC分类号： H03K21/00
摘要： A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.
摘要翻译： 用于在芯片上本地产生比率时钟的方法包括产生具有全局时钟周期的全局时钟信号。 集中式状态机包括响应于非整数数量的全局时钟周期的整个周期的计数器，状态机响应于计数器产生控制信号。 控制信号被提供给分段锁存器，分段锁存器产生时钟高信号和时钟低电平信号。 响应于全局时钟信号，时钟高电平信号和时钟低电平信号，本地通道门产生（n + 0.5）至1时钟信号。
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6.发明授权Circuits for locally generating non-integral divided clocks with centralized state machines 失效用集中式状态机本地生成非积分分时钟的电路公开(公告)号：US07319348B2
公开(公告)日：2008-01-15
申请号：US11341032
申请日：2006-01-27
IPC分类号： G06F1/04
CPC分类号： H03K23/502
摘要： Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles. The state machine generates a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal, the clock high signal and the clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high signal and the clock low signals have patterns that match the targeted divided clock frequency and duty cycle. A local pass gate receives the clock low signal and the clock high signal and generates an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.
摘要翻译： 本地生成芯片上的比率时钟的电路。 该电路包括用于产生具有全局时钟周期的全局时钟信号的电路。 状态机包括响应于非整数个全局时钟周期的整个周期的计数器。 状态机响应于计数器产生控制信号。 分段锁存器接收控制信号并产生时钟高信号和时钟低信号，时钟高信号和时钟低信号具有从目标分频比时钟的波形导出的模式，时钟高信号和时钟低信号具有 符合目标分频时钟频率和占空比的模式。 本地通过门接收时钟低电平信号和时钟高电平信号，并响应于全局时钟信号，时钟高电平信号和时钟低电平信号产生（n + 0.5）至1时钟信号。
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公开(公告)号：US08291157B2
公开(公告)日：2012-10-16
申请号：US12822364
申请日：2010-06-24
IPC分类号： G06F12/00
CPC分类号： G06F12/0846 , G06F12/0893
摘要： Concurrent refresh in a cache memory includes calculating a refresh time interval at a centralized refresh controller, the centralized refresh controller being common to all cache memory banks of the cache memory, transmitting a starting time of the refresh time interval to a bank controller, the bank controller being local to, and associated with, only one cache memory bank of the cache memory, sampling a continuous refresh status indicative of a number of refreshes necessary to maintain data within the cache memory bank associated with the bank controller, requesting a gap in a processing pipeline of the cache memory to facilitate the number of refreshes necessary, receiving a refresh grant in response to the requesting, and transmitting an encoded refresh command to the bank controller, the encoded refresh command indicating a number of refresh operations granted to the cache memory bank associated with the bank controller.
摘要翻译： 高速缓冲存储器中的并发刷新包括计算集中式刷新控制器的刷新时间间隔，集中式刷新控制器对于高速缓存存储器的所有高速缓存存储体共同，将刷新时间间隔的开始时间发送到银行控制器，银行 控制器本身并且仅与高速缓冲存储器的一个高速缓冲存储器组相关联，并且对与表示控制器相关联的高速缓存存储器中的数据进行维护所需的刷新次数的连续刷新状态进行采样，请求在 处理高速缓冲存储器的流水线以便于所需的刷新次数，响应于请求接收刷新许可，并向编组控制器发送编码的刷新命令，编码的刷新命令指示授予高速缓冲存储器的刷新操作的次数 与银行控制人有关的银行。
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8.发明申请公开(公告)号：US20110033017A1
公开(公告)日：2011-02-10
申请号：US12906658
申请日：2010-10-18
IPC分类号： H04L7/04
摘要： A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically. This invention resolves the uncertainty problem and allows the synchronization signals to be generated deterministically independent of the chip global clock cycle time.
摘要翻译： 一种用于产生多芯片系统的同步信号的时钟发生器电路。 时钟发生器电路包括从参考时钟和具有边缘检测逻辑的芯片全局时钟产生同步信号。 在具有多个芯片的高性能服务器系统设计中，服务器系统的常见做法是使用反馈时钟和延迟参考时钟来生成同步信号。 所产生的同步信号被传送到由全局时钟计时的锁存器，以用于芯片同步功能。 随着系统时钟频率被推高，由反馈时钟所产生的所生成的同步信号与由全局时钟计时的接收锁存器之间的相位差成为这个信号不能被确定地传送的循环时间的大部分。 本发明解决了不确定性问题，并允许确定地产生同步信号，而不依赖于芯片全局时钟周期时间。
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公开(公告)号：US20110320700A1
公开(公告)日：2011-12-29
申请号：US12822364
申请日：2010-06-24
IPC分类号： G06F12/06
CPC分类号： G06F12/0846 , G06F12/0893
摘要： Concurrent refresh in a cache memory includes calculating a refresh time interval at a centralized refresh controller, the centralized refresh controller being common to all cache memory banks of the cache memory, transmitting a starting time of the refresh time interval to a bank controller, the bank controller being local to, and associated with, only one cache memory bank of the cache memory, sampling a continuous refresh status indicative of a number of refreshes necessary to maintain data within the cache memory bank associated with the bank controller, requesting a gap in a processing pipeline of the cache memory to facilitate the number of refreshes necessary, receiving a refresh grant in response to the requesting, and transmitting an encoded refresh command to the bank controller, the encoded refresh command indicating a number of refresh operations granted to the cache memory bank associated with the bank controller.
摘要翻译： 高速缓冲存储器中的并发刷新包括计算集中式刷新控制器的刷新时间间隔，集中式刷新控制器对于高速缓存存储器的所有高速缓存存储体共同，将刷新时间间隔的开始时间发送到银行控制器，银行 控制器本身并且仅与高速缓冲存储器的一个高速缓冲存储器组相关联，并且对与表示控制器相关联的高速缓存存储器中的数据进行维护所需的刷新次数的连续刷新状态进行采样，请求在 处理高速缓冲存储器的流水线以便于所需的刷新次数，响应于请求接收刷新许可，并向编组控制器发送编码的刷新命令，编码的刷新命令指示授予高速缓冲存储器的刷新操作的次数 与银行控制人有关的银行。
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公开(公告)号：US07831946B2
公开(公告)日：2010-11-09
申请号：US11830910
申请日：2007-07-31
申请人： Rick L. Dennis , Charlie C. Hwang , Jose L. Neves
发明人： Rick L. Dennis , Charlie C. Hwang , Jose L. Neves
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62
摘要： A wiring structure for clock signals has two or more parallel clock signal wires disposed in adjacent power wire bays that span the distance between the sinks to which the clock signal wires are to be coupled. The parallel clock signal wires are shorted one to another by stubs placed at locations in order to time the clock wiring structure. The delay tuning of the structure is obtained by the discrete movement of wiring stubs between the wiring bays of the pre-defined power grid.
摘要翻译： 用于时钟信号的布线结构具有布置在相邻电源线托架中的两个或更多个并联时钟信号线，其跨越时钟信号线将耦合到的汇点之间的距离。 并行时钟信号线通过放置在位置处的短截线彼此短路，以便时钟布线结构。 结构的延迟调谐通过预定义电网的布线槽之间的布线短路的离散运动来获得。
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