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公开(公告)号：US07659740B2
公开(公告)日：2010-02-09
申请号：US12189226
申请日：2008-08-11
申请人： Joseph O. Marsh , Jeremy Stephens , Charlie C. Hwang , James S. Mason , Huihao Xu , Matthew B. Baecher , Thomas J. Bardsley , Mark R. Taylor
发明人： Joseph O. Marsh , Jeremy Stephens , Charlie C. Hwang , James S. Mason , Huihao Xu , Matthew B. Baecher , Thomas J. Bardsley , Mark R. Taylor
CPC分类号： G01R31/3167 , G01R31/318544
摘要： Digital testing of an analog driver circuit is enabled using a circuit including a control circuit for generating signals, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit, and a differential receiver circuit for converting the differential output signal to a single ended signal and transmitting the single ended signal. The testing includes skewing a differential output termination impedance, adjusting a differential receiver circuit voltage offset, selecting a differential driver circuit power level, enabling a decoder which activates only one differential driver circuit segment per test sequence, activating a segment, stimulating the differential driver circuit with digital test patterns, receiving differential driver circuit output, converting the output to a single-ended signal, and observing the single-ended signal.
摘要翻译： 使用包括用于产生信号的控制电路的电路，用于接收差分输入信号的差分驱动器电路，放大差分输入信号和发送差分输出信号来实现模拟驱动器电路的数字测试，用于产生可编程终端阻抗电路 在差分驱动电路的输出节点处的差分终端阻抗，以及用于将差分输出信号转换为单端信号并发送单端信号的差分接收电路。 测试包括偏移差分输出终端阻抗，调整差分接收器电路电压偏移，选择差分驱动器电路功率电平，使得能够在每个测试序列仅激活一个差分驱动器电路段的解码器，激活段，激励差分驱动器电路 具有数字测试模式，接收差分驱动电路输出，将输出转换为单端信号，并观察单端信号。
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公开(公告)号：US20090027075A1
公开(公告)日：2009-01-29
申请号：US12189226
申请日：2008-08-11
申请人： Joseph O. Marsh , Jeremy Stephens , Charlie C. Hwang , James S. Mason , Huihao Xu , Matthew B. Baecher , Thomas J. Bardsley , Mark R. Taylor
发明人： Joseph O. Marsh , Jeremy Stephens , Charlie C. Hwang , James S. Mason , Huihao Xu , Matthew B. Baecher , Thomas J. Bardsley , Mark R. Taylor
IPC分类号： G01R31/28
CPC分类号： G01R31/3167 , G01R31/318544
摘要： A circuit and method of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention comprises a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal. The method of the present invention comprises digitally testing the differential driver circuit by activating a test enable signal, skewing the differential output termination impedance in response to the test enable signal, adjusting a voltage offset of the differential receiver circuit in response to the test enable signal, selecting a power level for the differential driver circuit in response to the test enable signal, enabling a decoder in response to the test enable signal, wherein the decoder activates only one segment of the differential driver circuit during any one test sequence, activating one of the segments for testing, stimulating the differential driver circuit with digital test patterns, receiving an output of the differential driver circuit by the differential receiver circuit, converting the received differential driver output to a single-ended signal, observing the single-ended signal; and deactivating the test enable signal.
摘要翻译： 使用基于数字扫描的测试方法测试模拟驱动器电路的电路和方法。 本发明的电路包括用于响应于测试使能信号产生信号的控制电路，用于接收差分输入信号的差分驱动器电路，放大差分输入信号并响应差分输入信号发送差分输出信号 以及由所述控制电路产生的信号，用于响应于由所述控制电路产生的信号而在所述差分驱动器电路的输出节点处产生差分终端阻抗的可编程终端阻抗电路以及用于从所述差分接收电路接收所述差分输出的差分接收电路 差分驱动器电路将差分输出信号转换为单端信号并传输单端信号，全部是响应于测试使能信号。 本发明的方法包括通过激活测试使能信号来数字测试差分驱动器电路，响应于测试使能信号偏移差动输出终端阻抗，响应于测试使能信号调整差分接收器电路的电压偏移 ，响应于所述测试使能信号选择所述差分驱动器电路的功率电平，使能够响应于所述测试使能信号的解码器，其中所述解码器在任何一个测试序列期间仅激活所述差分驱动器电路的一个部分， 用于测试的段，用数字测试图案刺激差分驱动器电路，通过差分接收器电路接收差分驱动器电路的输出，将接收到的差分驱动器输出转换为单端信号，观察单端信号; 并禁用测试使能信号。
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公开(公告)号：US07466156B2
公开(公告)日：2008-12-16
申请号：US10708788
申请日：2004-03-25
申请人： Joseph O. Marsh , Jeremy Stephens , Charlie C. Hwang , James S. Mason , Huihao Xu , Matthew B. Baecher , Thomas J. Bardsley , Mark R. Taylor
发明人： Joseph O. Marsh , Jeremy Stephens , Charlie C. Hwang , James S. Mason , Huihao Xu , Matthew B. Baecher , Thomas J. Bardsley , Mark R. Taylor
IPC分类号： G01R31/02
CPC分类号： G01R31/3167 , G01R31/318544
摘要： A circuit of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention includes a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal.
摘要翻译： 使用基于数字扫描的测试方法测试模拟驱动器电路的电路。 本发明的电路包括用于响应于测试使能信号产生信号的控制电路，用于接收差分输入信号的差分驱动器电路，放大差分输入信号并响应差分输入信号发送差分输出信号 以及由所述控制电路产生的信号，用于响应于由所述控制电路产生的信号而在所述差分驱动器电路的输出节点处产生差分终端阻抗的可编程终端阻抗电路以及用于从所述差分接收电路接收所述差分输出的差分接收电路 差分驱动器电路将差分输出信号转换为单端信号并传输单端信号，全部是响应于测试使能信号。
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公开(公告)号：US07852151B2
公开(公告)日：2010-12-14
申请号：US12130453
申请日：2008-05-30
申请人： Thomas J. Bardsley , Matthew R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Gareth J. Nickolls
发明人： Thomas J. Bardsley , Matthew R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Gareth J. Nickolls
IPC分类号： H03F1/14
CPC分类号： H03F3/45475 , H03F1/0277 , H03F3/211 , H03F3/45179 , H03F3/72 , H03F2203/45138 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03G2201/103 , H03G2201/504
摘要： A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212). The gain of the amplifier array has a range from a low gain setting with a first amplifier stage (202) enabled, through increasing gain settings as the gain of the first amplifier stage is increased from a minimum to a maximum gain, a second amplifier stage (201) can then be enabled in addition to the first amplifier stage and the gain of the second amplifier stage increased from a minimum to a maximum gain, further amplifier stages are enabled as available up to a maximum gain setting for the amplifier array. Each amplifier stage that is enabled has a decreasingly attenuated input signal and a final amplifier stage to be enabled has a full input signal (203).
摘要翻译： 提供了改变放大器和放大器阵列的增益的方法。 放大器阵列包括与具有增益控制装置的每个放大器级并联连接的两个或更多个放大器级（201,202）。 为每个放大器级提供输入信号装置（203,204），放大器级的输入信号具有不同的幅度。 提供了用于启用和禁用放大器级（216）的装置，用于对使能的放大器级的输出进行求和以获得输出信号（212）的装置。 放大器阵列的增益具有从具有第一放大级（202）使能的低增益设置的范围，通过当第一放大器级的增益从最小增益增加到最大增益时增加增益设置，第二放大器级 （201）除了第一放大器级以及第二放大器级的增益从最小增益增加到最大增益之外，还可以使能另外的放大器级，直至达到放大器阵列的最大增益设置。 启用的每个放大器级具有递减衰减的输入信号，并且待使能的最终放大器级具有完整输入信号（203）。
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公开(公告)号：US20080284517A1
公开(公告)日：2008-11-20
申请号：US12130453
申请日：2008-05-30
申请人： Thomas J. Bardsley , Matthew R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Gareth J. Nicholls
发明人： Thomas J. Bardsley , Matthew R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Gareth J. Nicholls
IPC分类号： H03G3/10
CPC分类号： H03F3/45475 , H03F1/0277 , H03F3/211 , H03F3/45179 , H03F3/72 , H03F2203/45138 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03G2201/103 , H03G2201/504
摘要： A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212). The gain of the amplifier array has a range from a low gain setting with a first amplifier stage (202) enabled, through increasing gain settings as the gain of the first amplifier stage is increased from a minimum to a maximum gain, a second amplifier stage (201) can then be enabled in addition to the first amplifier stage and the gain of the second amplifier stage increased from a minimum to a maximum gain, further amplifier stages are enabled as available up to a maximum gain setting for the amplifier array. Each amplifier stage that is enabled has a decreasingly attenuated input signal and a final amplifier stage to be enabled has a full input signal (203).
摘要翻译： 提供了改变放大器和放大器阵列的增益的方法。 放大器阵列包括与具有增益控制装置的每个放大器级并联连接的两个或更多个放大器级（201,202）。 为每个放大器级提供输入信号装置（203,204），放大器级的输入信号具有不同的幅度。 提供了用于启用和禁用放大器级（216）的装置，用于对使能的放大器级的输出进行求和以获得输出信号（212）的装置。 放大器阵列的增益具有从具有第一放大级（202）使能的低增益设置的范围，通过当第一放大器级的增益从最小增益增加到最大增益时增加增益设置，第二放大器级 （201）除了第一放大器级以及第二放大器级的增益从最小增益增加到最大增益之外，还可以使能另外的放大器级，直至达到放大器阵列的最大增益设置。 启用的每个放大器级具有递减衰减的输入信号，并且待使能的最终放大器级具有完整输入信号（203）。
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公开(公告)号：US07397302B2
公开(公告)日：2008-07-08
申请号：US11734864
申请日：2007-04-13
申请人： Thomas J. Bardsley , Matthew R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Gareth J. Nicholls
发明人： Thomas J. Bardsley , Matthew R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Gareth J. Nicholls
IPC分类号： H03F1/14
CPC分类号： H03F3/45475 , H03F1/0277 , H03F3/211 , H03F3/45179 , H03F3/72 , H03F2203/45138 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03G2201/103 , H03G2201/504
摘要： A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212). The gain of the amplifier array has a range from a low gain setting with a first amplifier stage (202) enabled, through increasing gain settings as the gain of the first amplifier stage is increased from a minimum to a maximum gain, a second amplifier stage (201) can then be enabled in addition to the first amplifier stage and the gain of the second amplifier stage increased from a minimum to a maximum gain, further amplifier stages are enabled as available up to a maximum gain setting for the amplifier array. Each amplifier stage that is enabled has a decreasingly attenuated input signal and a final amplifier stage to be enabled has a full input signal (203).
摘要翻译： 提供了改变放大器和放大器阵列的增益的方法。 放大器阵列包括与具有增益控制装置的每个放大器级并联连接的两个或更多个放大器级（201,202）。 为每个放大器级提供输入信号装置（203,204），放大器级的输入信号具有不同的幅度。 提供了用于启用和禁用放大器级（216）的装置，用于对使能的放大器级的输出进行求和以获得输出信号（212）的装置。 放大器阵列的增益具有从具有第一放大级（202）使能的低增益设置的范围，通过当第一放大器级的增益从最小增益增加到最大增益时增加增益设置，第二放大器级 （201）除了第一放大器级以及第二放大器级的增益从最小增益增加到最大增益之外，还可以使能另外的放大器级，直至达到放大器阵列的最大增益设置。 启用的每个放大器级具有递减衰减的输入信号，并且待使能的最终放大器级具有完整输入信号（203）。
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公开(公告)号：US07250814B2
公开(公告)日：2007-07-31
申请号：US11096854
申请日：2005-04-01
申请人： Thomas J. Bardsley , Matthew R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Gareth J. Nicholls
发明人： Thomas J. Bardsley , Matthew R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Gareth J. Nicholls
IPC分类号： H03F1/14
CPC分类号： H03F3/45475 , H03F1/0277 , H03F3/211 , H03F3/45179 , H03F3/72 , H03F2203/45138 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03G2201/103 , H03G2201/504
摘要： A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212). The gain of the amplifier array has a range from a low gain setting with a first amplifier stage (202) enabled, through increasing gain settings as the gain of the first amplifier stage is increased from a minimum to a maximum gain, a second amplifier stage (201) can then be enabled in addition to the first amplifier stage and the gain of the second amplifier stage increased from a minimum to a maximum gain, further amplifier stages are enabled as available up to a maximum gain setting for the amplifier array. Each amplifier stage that is enabled has a decreasingly attenuated input signal and a final amplifier stage to be enabled has a full input signal (203).
摘要翻译： 提供了改变放大器和放大器阵列的增益的方法。 放大器阵列包括与具有增益控制装置的每个放大器级并联连接的两个或更多个放大器级（201,202）。 为每个放大器级提供输入信号装置（203,204），放大器级的输入信号具有不同的幅度。 提供了用于启用和禁用放大器级（216）的装置，用于对使能的放大器级的输出进行求和以获得输出信号（212）的装置。 放大器阵列的增益具有从具有第一放大级（202）使能的低增益设置的范围，通过当第一放大器级的增益从最小增益增加到最大增益时增加增益设置，第二放大器级 （201）除了第一放大器级以及第二放大器级的增益从最小增益增加到最大增益之外，还可以使能另外的放大器级，直至达到放大器阵列的最大增益设置。 启用的每个放大器级具有递减衰减的输入信号，并且待使能的最终放大器级具有完整输入信号（203）。
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公开(公告)号：US5754410A
公开(公告)日：1998-05-19
申请号：US710131
申请日：1996-09-11
申请人： Thomas J. Bardsley , Jed R. Eastman
发明人： Thomas J. Bardsley , Jed R. Eastman
IPC分类号： G01R1/04 , G01R31/28 , G01R31/317 , G01R31/3185 , H01L21/66 , H01L23/52 , H01L23/58 , H05K1/11 , H05K7/10 , H05K7/02
CPC分类号： H01L22/32 , G01R31/2884 , G01R31/31712 , G01R31/31715 , G01R31/318505 , G01R31/318513 , H05K7/1084 , G01R1/0408 , H01L2224/16225 , H01L2924/15174 , H01L2924/15192 , H01L2924/15312
摘要： An improved multi-chip-module having a substrate having top and bottom surfaces, a plurality of chips on the top surface, a plurality of pins on the bottom surface, each chip having at least one lead extending through the substrate and conductively coupled to a corresponding pin, the module having at least one net associated with the chips and completely embedded within the substrate, the improvement comprising at least one pad attached to the bottom surface of the substrate, and a conductive path conductively coupled between the pad and the net.
摘要翻译： 一种改进的多芯片模块，其具有具有顶表面和底表面的基板，顶表面上的多个芯片，底表面上的多个芯片，每个芯片具有延伸穿过基板的至少一个引线，并且导电耦合到 所述模块具有至少一个与所述芯片相关并且完全嵌入所述基板内的网，所述改进包括附接到所述基板的底表面的至少一个焊盘以及导电地耦合在所述焊盘和所述网之间的导电路径。
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公开(公告)号：US06834365B2
公开(公告)日：2004-12-21
申请号：US09907387
申请日：2001-07-17
IPC分类号： G06F1100
CPC分类号： G06F11/3636 , G06F11/3495
摘要： An integrated circuit real-time data tracing apparatus for analyzing microprocessor based computer systems for monitoring, in real-time, parameters sufficient to define the load and store operations information that the embedded core controller may assert, and process information during events. Integral on this single chip apparatus is a data trace unit designed to access control, address, and data signal lines required to monitor the embedded core controller's activities; perform data tracing independent of instruction tracing; synchronize with an instruction trace stream; allow for selection of multiple ranges for data tracing; report lost events to a FIFO array; and, output strobe signals to give a cycle accurate indication of when an event has been captured.
摘要翻译： 一种用于分析基于微处理器的计算机系统的集成电路实时数据跟踪装置，用于实时监测足以定义嵌入式核心控制器可以断言的负载和存储操作信息的参数，以及在事件期间处理信息。 该单芯片设备的一体是数据跟踪单元，用于访问监控嵌入式核心控制器活动所需的控制，地址和数据信号线; 执行独立于指令跟踪的数据跟踪; 与指令跟踪流同步; 允许选择多个范围进行数据跟踪; 将丢失的事件报告给FIFO数组; 并且输出选通信号以给出何时捕获事件的循环精确指示。
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公开(公告)号：US6094056A
公开(公告)日：2000-07-25
申请号：US35445
申请日：1998-03-05
申请人： Thomas J. Bardsley , Jed R. Eastman
发明人： Thomas J. Bardsley , Jed R. Eastman
IPC分类号： G01R1/04 , G01R31/28 , G01R31/317 , G01R31/3185 , H01L21/66 , H01L23/52 , H01L23/58 , H05K1/11 , H05K7/10 , G01R31/00
CPC分类号： H01L22/32 , G01R31/2884 , G01R31/31712 , G01R31/31715 , G01R31/318505 , G01R31/318513 , H05K7/1084 , G01R1/0408 , H01L2224/16225 , H01L2924/15174 , H01L2924/15192 , H01L2924/15312
摘要： A test fixture for use with an improved multi-chip-module wherein the multi-chip-module has a plurality of chips on the top surface, the module having at least one net associated with the chips completely embedded within the substrate and wherein at least one pad is attached to the bottom surface of the substrate and a conductive path provided between the pad and the net. The test fixture includes a zero-insertion-force socket having at least one socket pin having a surface for conductively contacting the pad on the multi-chip-module and extending through the socket and a circuit board having a plurality of inlets for conductively receiving the socket pins including the socket pin contacting the pad.
摘要翻译： 一种用于改进的多芯片模块的测试夹具，其中所述多芯片模块在顶表面上具有多个芯片，所述模块具有至少一个与完全嵌入所述基板内的所述芯片相关联的网，并且其中至少 一个焊盘附着到衬底的底表面和设置在焊盘和网之间的导电路径。 测试夹具包括具有至少一个插座销的零插入插座，所述插座销具有用于导电地接触多芯片模块上的焊盘并延伸穿过插座的表面，以及具有多个入口的电路板，用于导电地接收 插座销包括插座销接触垫。
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