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公开(公告)号：US4663545A
公开(公告)日：1987-05-05
申请号：US672539
申请日：1984-11-15
CPC分类号： G11C8/08 , H03K3/012 , H03K3/356078
摘要： A state machine in which the next state signals are biased by the next state encoder very close to the switch voltage of the input transistors of the present state latches to improve the response time of the state machine. Charge sharing on the outputs of the next state selector is prevented from affecting the biased next state signals by voltage substaining circuitry. By pre-encoding input signals pertinent to each state using separate input logic, the size of the next state selector is minimized, further improving the response time of the state machine. Selected present state latches may be prevented from changing state by gating the next state signals.
摘要翻译： 一种状态机，其中下一个状态信号被非常接近当前状态的输入晶体管的开关电压的下一个状态编码器偏置，以改善状态机的响应时间。 防止下一个状态选择器的输出上的电荷共享通过电压分配电路影响偏置的下一个状态信号。 通过使用单独的输入逻辑预编码与每个状态相关的输入信号，使下一状态选择器的大小最小化，进一步提高状态机的响应时间。 可以通过选通下一状态信号来防止选定的当前状态锁存器改变状态。
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2.发明授权Method and apparatus for shifting data in an array of storage elements in a data processing system 失效用于在数据处理系统中的存储元件阵列中的数据移位的方法和装置
公开(公告)号：US5369752A
公开(公告)日：1994-11-29
申请号：US891241
申请日：1992-06-01
CPC分类号： G11C7/1006 , G11C29/32
摘要： A method and apparatus for shifting data in an array of storage elements (22-37) in a data processing system (10). In one form, the present invention uses multiplexer (MUX) logic (38) and Shift Control signals to selectively couple storage elements (22-37) to latches (39-42). In this manner, data values can be serially scanned into and out of the array for test purposes without requiring a duplicate set of latches. The MUX logic 38 couples one storage element (22-37) to each latch (39-42). Then MUX logic 38 decouples those storage elements (22-37). Next, MUX logic 38 couples an adjacent storage element (22-37) to each latch (39-42). In this manner, the storage elements (22-37) in one row and the latches (39-42) mimic the functionality of a shift register.
摘要翻译： 一种用于在数据处理系统（10）中的存储元件阵列（22-37）中移位数据的方法和装置。 在一种形式中，本发明使用多路复用器（MUX）逻辑（38）和移位控制信号来选择性地将存储元件（22-37）耦合到锁存器（39-42）。 以这种方式，数据值可以串行扫描进出阵列用于测试目的，而不需要重复的锁存器组。 MUX逻辑38将一个存储元件（22-37）耦合到每个锁存器（39-42）。 然后MUX逻辑38解耦这些存储元件（22-37）。 接下来，MUX逻辑38将相邻存储元件（22-37）耦合到每个锁存器（39-42）。 以这种方式，一行中的存储元件（22-37）和锁存器（39-42）模拟移位寄存器的功能。
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公开(公告)号：US4749929A
公开(公告)日：1988-06-07
申请号：US945276
申请日：1986-12-22
IPC分类号： G05B19/045 , G05B11/32
CPC分类号： G05B19/045
摘要： Two state machines, each active during a respective one of two complementary non-overlapping clock phases, are interlocked so that the present state of one machine determines the next state of the other machine, and vice versa.
摘要翻译： 两个状态机在两个互补的不重叠的时钟相位中的相应的一个中相互活动，互锁，使得一个机器的当前状态确定另一个机器的下一个状态，反之亦然。
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公开(公告)号：US5001731A
公开(公告)日：1991-03-19
申请号：US415671
申请日：1989-10-02
摘要： A method and apparatus in an integrated circuit having a plurality of distinct circuit modules which eliminates undesired effects of clock skewing when a common system clock is used. The same phase of the same system clock is used by both a transmitting circuit module and a receiving circuit module when data is communicated between two circuit modules. The receiving circuit module has an input portion having a first transistor clocked by the same phase of the same system clock, a latch and a second transistor. The latch and second transistor are clocked by a complement of the same phase of the system clock.
摘要翻译： 具有多个不同电路模块的集成电路中的方法和装置，其在使用公共系统时钟时消除时钟偏移的不期望的影响。 当在两个电路模块之间传送数据时，发射电路模块和接收电路模块都使用相同系统时钟的相位。 接收电路模块具有输入部分，该输入部分具有由相同系统时钟相同相位的时钟的第一晶体管，锁存器和第二晶体管。 锁存器和第二晶体管由系统时钟相同相位的补码计时。
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公开(公告)号：US4398155A
公开(公告)日：1983-08-09
申请号：US273815
申请日：1981-06-15
IPC分类号： H03K17/693 , H03K5/26 , H03L7/00
CPC分类号： H03K17/693
摘要： A circuit for switching between multiple asynchronous clocks is provided. A synchronizer comprising D-type flip-flops, which are controlled by a clock change signal, are provided for each control signal being switched. Output signals provided by the synchronizers are used to control MOS transistor gates which switch the asynchronous clocks to the circuit output. The synchronizers also control a clamping transistor gate which clamps the circuit output to a reference during a switching operation. An additional synchronizer provides synchronization between the clock change signal and the circuit output allowing the circuit output to be interrupted at a known state.
摘要翻译： 提供了一种用于在多个异步时钟之间切换的电路。 为被切换的每个控制信号提供包括由时钟变化信号控制的D型触发器的同步器。 由同步器提供的输出信号用于控制将异步时钟切换到电路输出的MOS晶体管栅极。 同步器还控制钳位晶体管栅极，其在开关操作期间将电路输出钳位到参考电压。 另外的同步器提供时钟变化信号和电路输出之间的同步，允许在已知状态下中断电路输出。
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