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1.发明申请公开(公告)号：US20120144224A1
公开(公告)日：2012-06-07
申请号：US12960708
申请日：2010-12-06
IPC分类号： G06F1/08
摘要： Adjusting a clock source of a device clock to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The device clock may be derived from an input clock to a serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, it may be determined that the serial interface clock is or will interfere with wireless communication. Accordingly, temporary clock signals may be provided to the device clock while the first clock is modified. Once modified, the modified clock signals may be provided to the device clock to reduce wireless communication interference.
摘要翻译： 调整设备时钟的时钟源以减少设备内的无线通信（例如射频（RF））干扰。 设备时钟可以从例如耦合到显示器的串行接口的输入时钟导出，并且可以最初由第一时钟驱动。 之后，可以确定串行接口时钟是或将会干扰无线通信。 因此，在修改第一时钟的同时，可以将临时时钟信号提供给设备时钟。 一旦被修改，修改的时钟信号可以被提供给设备时钟以减少无线通信干扰。
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2.发明授权公开(公告)号：US08417983B2
公开(公告)日：2013-04-09
申请号：US12960708
申请日：2010-12-06
IPC分类号： G06F1/00 , G06F1/04 , G06F3/033 , H03K3/03 , H03K19/00 , H03K9/00 , H03B25/00 , H04L27/00 , H04H20/71 , H04B1/38
摘要： Adjusting a clock source of a device clock to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The device clock may be derived from an input clock to a serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, it may be determined that the serial interface clock is or will interfere with wireless communication. Accordingly, temporary clock signals may be provided to the device clock while the first clock is modified. Once modified, the modified clock signals may be provided to the device clock to reduce wireless communication interference.
摘要翻译： 调整设备时钟的时钟源以减少设备内的无线通信（例如射频（RF））干扰。 设备时钟可以从例如耦合到显示器的串行接口的输入时钟导出，并且可以最初由第一时钟驱动。 之后，可以确定串行接口时钟是或将会干扰无线通信。 因此，在修改第一时钟的同时，可以将临时时钟信号提供给设备时钟。 一旦被修改，修改的时钟信号可以被提供给设备时钟以减少无线通信干扰。
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公开(公告)号：US20120185703A1
公开(公告)日：2012-07-19
申请号：US13006967
申请日：2011-01-14
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： Systems and methods for coordinating performance parameters in multiple domains are described. In an embodiment, a method includes receiving a request to change a state of an electronic circuit, where the circuit includes a first domain and a second domain, causing a first parameter of a first circuit serving the first domain to be modified to a first modified parameter based on the request, and causing a second parameter of a second circuit serving the second domain to be modified to a second modified parameter based on the request. In some cases, a parameter may include a clock frequency. In other cases, a parameter may include a voltage. In some embodiments, a system may be implemented as a logic circuit and/or as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.
摘要翻译： 描述用于协调多个域中的性能参数的系统和方法。 在一个实施例中，一种方法包括接收改变电子电路的状态的请求，其中电路包括第一域和第二域，使得服务于第一域的第一电路的第一参数被修改为第一修改 参数，并且基于该请求，使服务于第二域的第二电路的第二参数被修改为第二修改参数。 在一些情况下，参数可以包括时钟频率。 在其他情况下，参数可以包括电压。 在一些实施例中，系统可以被实现为逻辑电路和/或作为片上系统（SoC）。 适用于这些系统的设备包括例如台式和膝上型计算机，平板电脑，网络设备，移动电话，个人数字助理，电子书阅读器，电视机和游戏机。
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公开(公告)号：US20120084589A1
公开(公告)日：2012-04-05
申请号：US12894516
申请日：2010-09-30
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3275 , G06F1/3287 , G06F12/0802 , G06F2212/1028 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.
摘要翻译： 在一个实施例中，控制电路被配置为向断电后正在上电的电路块传送操作，以重新初始化电路块以进行操作。 操作可以存储在控制电路耦合到的存储器（例如一组寄存器）中。 在一个实施例中，控制电路还可以被配置为在电路块断电之前将其他操作从存储器传送到电路块。 因此，即使在系统中的处理器断电（并且因此软件不可执行的时候），即使在唤醒处理器以进行上电/断电事件的时间内，电路块也可以上电或掉电。 在一个实施例中，电路块可以是耦合到一个或多个处理器的高速缓存器。
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5.发明授权Systems and method for hardware dynamic cache power management via bridge and power manager 有权通过桥和电源管理器进行硬件动态高速缓存电源管理的系统和方法公开(公告)号：US08806232B2
公开(公告)日：2014-08-12
申请号：US12894516
申请日：2010-09-30
CPC分类号： G06F1/3203 , G06F1/3275 , G06F1/3287 , G06F12/0802 , G06F2212/1028 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.
摘要翻译： 在一个实施例中，控制电路被配置为向断电后正在上电的电路块传送操作，以重新初始化电路块以进行操作。 操作可以存储在控制电路耦合到的存储器（例如一组寄存器）中。 在一个实施例中，控制电路还可以被配置为在电路块断电之前将其他操作从存储器传送到电路块。 因此，即使在系统中的处理器断电（并且因此软件不可执行的时候），即使在唤醒处理器以进行上电/断电事件的时间内，电路块也可以上电或掉电。 在一个实施例中，电路块可以是耦合到一个或多个处理器的高速缓存器。
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6.发明授权Modifying performance parameters in multiple circuits according to a performance state table upon receiving a request to change a performance state 有权在接收到改变性能状态的请求时，根据性能状态表来修改多个电路中的性能参数公开(公告)号：US08468373B2
公开(公告)日：2013-06-18
申请号：US13006967
申请日：2011-01-14
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： Systems and methods for coordinating performance parameters in multiple domains are described. In an embodiment, a method includes receiving a request to change a state of an electronic circuit, where the circuit includes a first domain and a second domain, causing a first parameter of a first circuit serving the first domain to be modified to a first modified parameter based on the request, and causing a second parameter of a second circuit serving the second domain to be modified to a second modified parameter based on the request. In some cases, a parameter may include a clock frequency. In other cases, a parameter may include a voltage. In some embodiments, a system may be implemented as a logic circuit and/or as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.
摘要翻译： 描述用于协调多个域中的性能参数的系统和方法。 在一个实施例中，一种方法包括接收改变电子电路的状态的请求，其中电路包括第一域和第二域，使得服务于第一域的第一电路的第一参数被修改为第一修改 参数，并且基于该请求，使服务于第二域的第二电路的第二参数被修改为第二修改参数。 在一些情况下，参数可以包括时钟频率。 在其他情况下，参数可以包括电压。 在一些实施例中，系统可以被实现为逻辑电路和/或作为片上系统（SoC）。 适用于这些系统的设备包括例如台式和膝上型计算机，平板电脑，网络设备，移动电话，个人数字助理，电子书阅读器，电视机和游戏机。
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公开(公告)号：US09032113B2
公开(公告)日：2015-05-12
申请号：US12057146
申请日：2008-03-27
CPC分类号： G06F13/34 , G06F1/12 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F1/3287 , G06F13/1673 , G06F13/28 , Y02D10/126 , Y02D10/151 , Y02D10/171
摘要： A method and system is disclosed for accessing I/O and memory devices utilizing a DMA controller. Each device may be connected to the DMA controller through an individual channel. Clocking circuitry in the DMA may allow the DMA controller to send signals to each device at a prescribed frequency. Furthermore, the DMA controller is capable of activating and deactivating a channel clock, used in sending signals to the devices, based on the operational status of the individual devices. The DMA controller is also capable of tuning the channel clock dependant on the capabilities of any active devices. In this manner, the amount of bandwidth used during a DMA data transfer can be tailored to the specific requirements of the devices involved with the data transfer.
摘要翻译： 公开了一种利用DMA控制器访问I / O和存储器件的方法和系统。 每个设备可以通过单独的通道连接到DMA控制器。 DMA中的时钟电路可以允许DMA控制器以规定的频率向每个设备发送信号。 此外，DMA控制器能够基于各个设备的操作状态来激活和去激活用于向设备发送信号的通道时钟。 DMA控制器还能够根据任何有源器件的功能调整通道时钟。 以这种方式，DMA数据传输期间使用的带宽量可以根据与数据传输相关的设备的具体要求进行调整。
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公开(公告)号：US08855459B2
公开(公告)日：2014-10-07
申请号：US12140976
申请日：2008-06-17
CPC分类号： G06F1/30 , G06F1/3203
摘要： A method of operating a media player is provided. In one embodiment the method includes receiving a plurality of initially configured video settings for viewing a video segment on the media player for a desired playback duration. The method further includes determining power required to play the video segment based on the initial video settings and playing the video segment if the required power matches or is less than total power available to the media player. In another embodiment, the method may further include, if the required power exceeds the total power available to the media player, adjusting one or more of the initial video settings, either automatically or by user inputs, to reduce the power required to play the requested video segment for the desired playback duration.
摘要翻译： 提供操作媒体播放器的方法。 在一个实施例中，该方法包括接收多个初始配置的视频设置，用于在媒体播放器上观看期望的播放持续时间的视频段。 该方法还包括：如果所需功率匹配或小于媒体播放器可用的总功率，则基于初始视频设置确定播放视频片段所需的功率并播放视频片段。 在另一个实施例中，如果所需功率超过媒体播放器可用的总功率，该方法可以进一步包括：自动地或通过用户输入来调整一个或多个初始视频设置，以减少播放所请求的功率所需的功率 视频段用于所需播放持续时间。
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9.发明授权公开(公告)号：US08443216B2
公开(公告)日：2013-05-14
申请号：US13590217
申请日：2012-08-21
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/17 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.
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公开(公告)号：US08392658B2
公开(公告)日：2013-03-05
申请号：US12500768
申请日：2009-07-10
申请人： James Wang , Zongjian Chen , James B. Keller , Timothy J. Millet
发明人： James Wang , Zongjian Chen , James B. Keller , Timothy J. Millet
IPC分类号： G06F12/00
CPC分类号： G06F12/128 , G06F12/0864 , G06F12/121 , G06F12/123
摘要： In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy.
摘要翻译： 在一个实施例中，高速缓存存储存储在高速缓存中的高速缓存块的标签。 每个标签可以包括标识由高速缓存支持的两个或多个替换策略中哪一个正在用于对应的高速缓存块的指示，以及指示替换策略中对应的高速缓存块的状态的替换记录。 请求可以包括标识用于请求访问的高速缓存块的期望替换策略的替换属性。 如果请求是高速缓存中的错过，则可以分配高速缓存块存储位置以存储对应的高速缓存块。 与高速缓存块存储位置相关联的标签可以被更新以包括期望的替换策略的指示，并且高速缓存可以根据策略来管理块。 例如，在一个实施例中，高速缓存可以支持LRR和LRU策略。
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