公开(公告)号：US20110044121A1

公开(公告)日：2011-02-24

申请号：US12860484

申请日：2010-08-20

申请人： Joung-Yeal Kim ,  Soo-Bong Chang ,  Seong-Jin Jang ,  Jin-Seok Kwak ,  Dong-Hak Shin

发明人： Joung-Yeal Kim ,  Soo-Bong Chang ,  Seong-Jin Jang ,  Jin-Seok Kwak ,  Dong-Hak Shin

IPC分类号： G11C7/06

CPC分类号： G11C11/4094 ,  G11C11/4091 ,  G11C2207/005

摘要： A semiconductor memory device includes a memory cell array block including a plurality of memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines, a sense amplifier connected to a half of the plurality of bit lines, the sense amplifier for sensing and amplifying a voltage between each of the half of the bit lines and a corresponding complementary bit line; and a dummy block connected to the half of the plurality of bit lines of the memory cell array block, the dummy block for controlling a load on the memory cell array block to be different from a load on the dummy block according to a dummy load signal.

摘要翻译： 半导体存储器件包括存储单元阵列块，该存储单元阵列块包括多个存储单元，每个存储单元分别连接到多个位线中的一个位线和多个字线中的一个，连接到多个位线的一半的读出放大器， 读出放大器，用于感测和放大位线的每一个之间的电压和相应的互补位线; 以及连接到存储单元阵列块的多个位线的一半的虚拟块，用于根据虚拟负载信号控制存储单元阵列块上的负载与虚拟块上的负载不同的虚拟块 。

公开(公告)号：US20090207674A1

公开(公告)日：2009-08-20

申请号：US12372290

申请日：2009-02-17

申请人： Soo-Bong Chang ,  Doo-Young Kim ,  Jung-Im Huh

发明人： Soo-Bong Chang ,  Doo-Young Kim ,  Jung-Im Huh

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C5/147

摘要： A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.

摘要翻译： 提供半导体存储器件和在半导体存储器件中产生内部电压的方法。 半导体存储器件包括：控制器，被配置为当从外部施加有效命令时激活感测使能信号，当施加预充电命令时使感测使能信号失效，并输出感测使能信号;以及阵列内部电压发生器，被配置为 当感测使能信号被激活时，输出有源阵列电源电压作为阵列电源电压，当感测使能信号被去激活时，输出外部阵列电源电压和备用阵列电源电压作为阵列电源电压;以及 当感测使能信号在至少特定的时间段内被去激活时，单独输出备用阵列电源电压作为阵列电源电压。

公开(公告)号：US20060163613A1

公开(公告)日：2006-07-27

申请号：US11336831

申请日：2006-01-23

申请人： Soo-Bong Chang ,  In-Chul Jeong ,  Jun-Hyung Kim ,  Seung-Min Oh ,  Jung-Hwa Lee

发明人： Soo-Bong Chang ,  In-Chul Jeong ,  Jun-Hyung Kim ,  Seung-Min Oh ,  Jung-Hwa Lee

IPC分类号： H01L27/10

CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/11898

摘要： A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross sectional length, the N-channel transistor arrangement oriented such that the cross sectional length extends along a first direction, the first direction oriented along a sub word line driver from a first sub array block to a second sub array block. The example method may arrange the at least one N-channel transistor between the first and second sub array blocks.

摘要翻译： 子字线驱动器的布局结构及其方法。 示例性布局结构可以包括具有横截面宽度和横截面长度的至少一个N沟道晶体管布置，N沟道晶体管布置方向使得横截面长度沿着第一方向延伸，第一方向沿着第一方向 子字线驱动器从第一子阵列块到第二子阵列块。 该示例性方法可以在第一和第二子阵列块之间布置至少一个N沟道晶体管。

公开(公告)号：US20120213018A1

公开(公告)日：2012-08-23

申请号：US13462915

申请日：2012-05-03

申请人： Soo-Bong Chang ,  Doo-Young Kim ,  Jung-Im Huh

发明人： Soo-Bong Chang ,  Doo-Young Kim ,  Jung-Im Huh

IPC分类号： G11C7/00

CPC分类号： G11C5/147

摘要： A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.

摘要翻译： 提供半导体存储器件和在半导体存储器件中产生内部电压的方法。 半导体存储器件包括：控制器，被配置为当从外部施加有效命令时激活感测使能信号，当施加预充电命令时使感测使能信号失效，并输出感测使能信号;以及阵列内部电压发生器，被配置为 当感测使能信号被激活时，输出有源阵列电源电压作为阵列电源电压，当感测使能信号被去激活时，输出外部阵列电源电压和备用阵列电源电压作为阵列电源电压;以及 当感测使能信号在至少特定的时间段内被去激活时，单独输出备用阵列电源电压作为阵列电源电压。

公开(公告)号：US07075849B2

公开(公告)日：2006-07-11

申请号：US10786855

申请日：2004-02-24

申请人： Soo-Bong Chang ,  Jung-Hwa Lee ,  Chi-Wook Kim ,  Byong-Mo Moon

发明人： Soo-Bong Chang ,  Jung-Hwa Lee ,  Chi-Wook Kim ,  Byong-Mo Moon

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C5/14

摘要： Embodiments of the invention provide drivers from active internal voltage generating circuits on both sides of the internal voltage generating lines, therefore a voltage level of the internal voltage generating lines can quickly and uniformly reach a desired internal voltage level. Other embodiments of the invention are described in the claims.

摘要翻译： 本发明的实施例提供了内部电压发生线两侧的有源内部电压产生电路的驱动器，因此内部电压发生线的电压电平可以快速均匀地达到期望的内部电压电平。 在权利要求中描述了本发明的其它实施例。

公开(公告)号：US08189406B2

公开(公告)日：2012-05-29

申请号：US12978677

申请日：2010-12-27

申请人： Soo-Bong Chang ,  Doo-Young Kim ,  Jung-Im Huh

发明人： Soo-Bong Chang ,  Doo-Young Kim ,  Jung-Im Huh

IPC分类号： G11C5/14

CPC分类号： G11C5/147

摘要： A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.

摘要翻译： 提供半导体存储器件和在半导体存储器件中产生内部电压的方法。 半导体存储器件包括：控制器，被配置为当从外部施加有效命令时激活感测使能信号，当施加预充电命令时使感测使能信号失效，并输出感测使能信号;以及阵列内部电压发生器，被配置为 当感测使能信号被激活时，输出有源阵列电源电压作为阵列电源电压，当感测使能信号被去激活时，输出外部阵列电源电压和备用阵列电源电压作为阵列电源电压;以及 当感测使能信号在至少特定的时间段内被去激活时，单独输出备用阵列电源电压作为阵列电源电压。

公开(公告)号：US07336518B2

公开(公告)日：2008-02-26

申请号：US11383727

申请日：2006-05-16

申请人： Soo-Bong Chang ,  Chi-Wook Kim

发明人： Soo-Bong Chang ,  Chi-Wook Kim

IPC分类号： G11C5/02

CPC分类号： G11C7/1048 ,  G11C7/062 ,  G11C11/4091 ,  G11C11/4093

摘要： A memory device includes a memory cell array block including memory cells, a word line driver block adjacent the memory cell array block disposed in a direction in which word lines of the memory cells are arranged, a sense amplifier block adjacent the memory cell array block disposed in a direction in which bit lines of the memory cells are arranged, a conjunction block disposed at an intersection of the word line driver block and the sense amplifier block, an equalizer for equalizing a pair of local data lines, the equalizer disposed in the conjunction block, and a local data line sense amplifier configured to sense and amplify signals on a pair of local data lines, and having transistors of a first type disposed in the conjunction block and transistors of a second type disposed in the sense amplifier block.

摘要翻译： 存储器件包括存储单元阵列块，存储单元阵列块，与沿着存储单元的字线排列的方向布置的存储单元阵列块相邻的字线驱动块，设置有存储单元阵列块的读出放大器块 在布置存储单元的位线的方向上，设置在字线驱动块和读出放大器块的交叉点处的连接块，用于均衡一对本地数据线的均衡器，均衡器配置在一起 块和本地数据线读出放大器，其被配置为感测和放大一对本地数据线上的信号，并且具有布置在连接块中的第一类型的晶体管和布置在读出放大器块中的第二类型的晶体管。

公开(公告)号：US07359280B2

公开(公告)日：2008-04-15

申请号：US11336831

申请日：2006-01-23

申请人： Soo-Bong Chang ,  In-Chul Jeong ,  Jun-Hyung Kim ,  Seung-Min Oh ,  Jung-Hwa Lee

发明人： Soo-Bong Chang ,  In-Chul Jeong ,  Jun-Hyung Kim ,  Seung-Min Oh ,  Jung-Hwa Lee

IPC分类号： G11C8/00

CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/11898

摘要： A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross sectional length, the N-channel transistor arrangement oriented such that the cross sectional length extends along a first direction, the first direction oriented along a sub word line driver from a first sub array block to a second sub array block. The example method may arrange the at least one N-channel transistor between the first and second sub array blocks.

摘要翻译： 子字线驱动器的布局结构及其方法。 示例性布局结构可以包括具有横截面宽度和横截面长度的至少一个N沟道晶体管布置，N沟道晶体管布置方向使得横截面长度沿着第一方向延伸，第一方向沿着第一方向 子字线驱动器从第一子阵列块到第二子阵列块。 该示例性方法可以在第一和第二子阵列块之间布置至少一个N沟道晶体管。

公开(公告)号：US20060146618A1

公开(公告)日：2006-07-06

申请号：US11313722

申请日：2005-12-22

申请人： Soo-Bong Chang ,  Chi-Wook Kim

发明人： Soo-Bong Chang ,  Chi-Wook Kim

IPC分类号： G11C7/00

CPC分类号： G11C5/145 ,  G11C11/406 ,  G11C11/4074 ,  G11C2211/4065

摘要： In a boosted voltage generating circuit of a semiconductor memory device, an active kicker drive signal generating circuit generates an active kicker drive signal having a first pulse duration in response to a row active command, and generates the active kicker drive signal having a second pulse duration in response to a refresh command. An active kicker circuit is responsive to the active kicker drive signal to generate the boosted voltage. The second pulse duration may be greater than the first pulse duration, which makes it possible to improve the pumping efficiency of the boosted voltage in a refresh operation.

摘要翻译： 在半导体存储器件的升压电压产生电路中，有源icker驱动信号发生电路响应于行有效命令产生具有第一脉冲持续时间的有效icker驱动信号，并产生具有第二脉冲持续时间 响应刷新命令。 有源激光电路响应于激活的激光驱动信号以产生升压电压。 第二脉冲持续时间可以大于第一脉冲持续时间，这使得可以在刷新操作中提高升压电压的泵送效率。

公开(公告)号：US07864599B2

公开(公告)日：2011-01-04

申请号：US12372290

申请日：2009-02-17

申请人： Soo-Bong Chang ,  Doo-Young Kim ,  Jung-Im Huh

发明人： Soo-Bong Chang ,  Doo-Young Kim ,  Jung-Im Huh

IPC分类号： G11C5/14

CPC分类号： G11C5/147

摘要： A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.

摘要翻译： 提供半导体存储器件和在半导体存储器件中产生内部电压的方法。 半导体存储器件包括：控制器，被配置为当从外部施加有效命令时激活感测使能信号，当施加预充电命令时使感测使能信号失效，并输出感测使能信号;以及阵列内部电压发生器，被配置为 当感测使能信号被激活时，输出有源阵列电源电压作为阵列电源电压，当感测使能信号被去激活时，输出外部阵列电源电压和备用阵列电源电压作为阵列电源电压;以及 当感测使能信号在至少特定的时间段内被去激活时，单独输出备用阵列电源电压作为阵列电源电压。