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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07372766B2

    公开(公告)日：2008-05-13

    申请号：US11496401

    申请日：2006-08-01

    Applicant: Ki-Won Park ,  Dong-Hak Shin

    Inventor： Ki-Won Park ,  Dong-Hak Shin

    IPC: G11C8/00

    CPC classification number: G11C11/4096 ,  G11C2207/002

    Abstract: A semiconductor memory device may include a switching unit to selectively connect a bitline pair and a pair of input/output lines in response to a column selection line signal; a column selection line voltage generator to generate a column selection line voltage; and a column selection line driver to provide the column selection line signal based at least in at the column selection line voltage level.

    Abstract translation: 半导体存储器件可以包括：切换单元，用于响应于列选择线信号选择性地连接位线对和一对输入/输出线; 列选择线电压发生器，以产生列选择线电压; 以及列选择线驱动器，用于至少在列选择线电压电平上提供列选择线信号。

    Semiconductor memory device
    2.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20060120177A1

    公开(公告)日：2006-06-08

    申请号：US11267805

    申请日：2005-11-04

    Applicant: Dong-Hak Shin

    Inventor： Dong-Hak Shin

    IPC: G11C5/14

    CPC classification number: G11C11/417 ,  G11C5/145

    Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cell array blocks in turn including first and second memory cell array blocks, the number of word lines activated when the first memory cell array blocks are selected being greater than the number of word lines activated when the second memory cell array blocks are selected; a first boosting voltage generating portion generating a first driving signal when the semiconductor device operates in an active mode and supplying a boosting voltage that is higher than a power supply voltage to an output terminal in response to the first driving signal; and a second boosting voltage generating portion including first and second boosting voltage generators, the first boosting voltage generator generating a second driving signal when a level of the boosting voltage of the output terminal is below a target level in the active mode and pumping the boosting voltage in response to the second driving signal, the second boosting voltage generator pumping the boosting voltage in response to the first driving signal when the first memory cell array blocks are selected and pumping the boosting voltage in response to the second driving signal when the second memory cell array blocks are selected. Thus, the semiconductor memory device can constantly maintain the level of the boosting voltage regardless of the location of the selected memory cell array block, thereby preventing reduction of device life span or degradation of characteristics resulting from drop in the boosting voltage.

    Abstract translation: 半导体存储器件包括：包括多个存储单元阵列块的存储单元阵列，其又包括第一和第二存储单元阵列块，当选择第一存储单元阵列块时激活的字线数量大于 当选择第二存储单元阵列块时激活字线; 第一升压电压产生部分，当所述半导体器件以活动模式工作时产生第一驱动信号，并且响应于所述第一驱动信号向输出端提供高于电源电压的升压电压; 以及包括第一和第二升压电压发生器的第二升压电压产生部分，当所述输出端子的升压电压的电平低于所述激活模式中的目标电平时，所述第一升压电压发生器产生第二驱动信号，并且将所述升压电压 响应于第二驱动信号，第二升压电压发生器在选择第一存储单元阵列块时响应于第一驱动信号而泵浦升压电压，并且当第二存储器单元响应于第二驱动信号而泵送升压电压 选择阵列块。 因此，无论选择的存储单元阵列块的位置如何，半导体存储器件可以恒定地保持升压电压的水平，从而防止器件寿命的缩短或由升压电压下降引起的特性的降低。

    SEMICONDUCTOR MEMORY DEVICE HAVING DEVICE FOR CONTROLLING BIT LINE LOADING AND IMPROVING SENSING EFFICIENCY OF BIT LINE SENSE AMPLIFIER
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING DEVICE FOR CONTROLLING BIT LINE LOADING AND IMPROVING SENSING EFFICIENCY OF BIT LINE SENSE AMPLIFIER 审中-公开
    具有用于控制位线负载的设备的半导体存储器件和提高位线感测放大器的感测效率

    公开(公告)号：US20110044121A1

    公开(公告)日：2011-02-24

    申请号：US12860484

    申请日：2010-08-20

    Applicant: Joung-Yeal Kim ,  Soo-Bong Chang ,  Seong-Jin Jang ,  Jin-Seok Kwak ,  Dong-Hak Shin

    Inventor： Joung-Yeal Kim ,  Soo-Bong Chang ,  Seong-Jin Jang ,  Jin-Seok Kwak ,  Dong-Hak Shin

    IPC: G11C7/06

    CPC classification number: G11C11/4094 ,  G11C11/4091 ,  G11C2207/005

    Abstract: A semiconductor memory device includes a memory cell array block including a plurality of memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines, a sense amplifier connected to a half of the plurality of bit lines, the sense amplifier for sensing and amplifying a voltage between each of the half of the bit lines and a corresponding complementary bit line; and a dummy block connected to the half of the plurality of bit lines of the memory cell array block, the dummy block for controlling a load on the memory cell array block to be different from a load on the dummy block according to a dummy load signal.

    Abstract translation: 半导体存储器件包括存储单元阵列块，该存储单元阵列块包括多个存储单元，每个存储单元分别连接到多个位线中的一个位线和多个字线中的一个，连接到多个位线的一半的读出放大器， 读出放大器，用于感测和放大位线的每一个之间的电压和相应的互补位线; 以及连接到存储单元阵列块的多个位线的一半的虚拟块，用于根据虚拟负载信号控制存储单元阵列块上的负载与虚拟块上的负载不同的虚拟块 。

    Optical cross-connect device
    6.
    发明授权
    Optical cross-connect device 失效
    光交叉设备

    公开(公告)号：US07013060B2

    公开(公告)日：2006-03-14

    申请号：US11182143

    申请日：2005-07-15

    Applicant: Teruya Sugiyama ,  Mitsuteru Inoue ,  Dong-Hak Shin ,  Hitoshi Masuda

    Inventor： Teruya Sugiyama ,  Mitsuteru Inoue ,  Dong-Hak Shin ,  Hitoshi Masuda

    IPC: G02B6/26 ,  G02B6/42

    CPC classification number: G02B5/32 ,  G02B6/3556 ,  G02B6/356 ,  G02F1/0338 ,  G11C13/042 ,  H04Q11/0005 ,  H04Q2011/0028 ,  H04Q2011/0035 ,  H04Q2011/0039

    Abstract: An optic switch for cross-connecting input light signals incoming from inlet fiber cables to outlet fiber cables is disclosed that makes use of a holographic filter (5) having a series of preformed different speckle patterns, each in the form of a hologram (H1, H2, . . . ). Associated with input light signals guided past respective inlet passages (4in) of a multimode waveguide (4), different speckle patterns are formed by applying different control voltages across respective electrode pairs (10, 10a) provided thereon. These speckle patterns past a single outlet passage (4out) of the multimode waveguide (4) into which the inlet passages (4in) converge are joined together and enter the holographic filter (5) in which an input light signal is selectively switched, addressed and cross-connected to an outlet waveguide (2) through a region thereof where a formed speckle pattern coincides with a preformed speckle pattern. The multi mode waveguides (4) is formed in, e.g., a LiNbO3 photorefractive substrate (3).

    Abstract translation: 公开了一种用于交叉连接从入口光缆到出口光纤电缆的输入光信号的光开关，其利用具有一系列预制的不同散斑图案的全息滤光片（5），每个都具有全息图形式（H < SUB> 1，H 2，...，...）。 与通过多模波导（4）的相应入口通道（4 in）引导的输入光信号相关联，通过在其上提供的各个电极对（10,10a）施加不同的控制电压来形成不同的散斑图案。 通过入口通道（4 in）会聚在其中的多模波导（4）的单个出口通道（4 out）上的这些斑点图案被连接在一起并进入选择性地切换输入光信号的全息滤光器（5） 寻址并通过其出口波导（2）交叉连接，其中形成的斑点图案与预先形成的斑点图案重合。 多模波导（4）形成在例如LiNbO 3光折射基板（3）中。

    MEMORY DEVICE EMPLOYING OPEN BIT LINE ARCHITECTURE FOR PROVIDING IDENTICAL DATA TOPOLOGY ON REPAIRED MEMORY CELL BLOCK AND METHOD THEREOF
    7.
    发明申请
    MEMORY DEVICE EMPLOYING OPEN BIT LINE ARCHITECTURE FOR PROVIDING IDENTICAL DATA TOPOLOGY ON REPAIRED MEMORY CELL BLOCK AND METHOD THEREOF 失效
    使用开放位线架构的记忆装置，用于在修复的记忆体块上提供标识数据拓扑及其方法

    公开(公告)号：US20060028900A1

    公开(公告)日：2006-02-09

    申请号：US11197227

    申请日：2005-08-04

    Applicant: Dong-Hak Shin ,  Ho-Sung Song ,  Byung-Sik Moon

    Inventor： Dong-Hak Shin ,  Ho-Sung Song ,  Byung-Sik Moon

    IPC: G11C8/00 ,  G11C7/06 ,  G11C29/00

    CPC classification number: G11C7/18 ,  G11C29/808 ,  G11C29/846

    Abstract: A memory device has at least one pair of memory cell blocks, a spare row decoder, a data exchange control signal generator and a data exchange unit. When a defective memory cell in a first memory cell block is repaired with a spare memory cell in a second memory cell block that neighbors (or is adjacent) the first memory cell block, the data topology of the memory cell of the first memory cell may be matched to the memory cell of the second memory cell block.

    Abstract translation: 存储器件具有至少一对存储单元块，备用行解码器，数据交换控制信号发生器和数据交换单元。 当第一存储器单元块中的有缺陷的存储器单元用邻近（或相邻）第一存储器单元块的第二存储器单元块中的备用存储器单元修复时，第一存储器单元的存储单元的数据拓扑可以 与第二存储单元块的存储单元匹配。

    Apparatus and method for watermarking using elemental images of integrated image having three-dimensional information
    8.
    发明授权
    Apparatus and method for watermarking using elemental images of integrated image having three-dimensional information 失效
    使用具有三维信息的集成图像的元素图像进行水印加密的装置和方法

    公开(公告)号：US07936899B2

    公开(公告)日：2011-05-03

    申请号：US11880224

    申请日：2007-07-19

    Applicant: Eun-Soo Kim ,  Dong-Choon Hwang ,  Dong-Hak Shin

    Inventor： Eun-Soo Kim ,  Dong-Choon Hwang ,  Dong-Hak Shin

    IPC: G06K9/00 ,  G06K9/36

    CPC classification number: H04N1/32154 ,  G06T1/0021 ,  G06T2201/0052 ,  H04N1/3217 ,  H04N13/261 ,  H04N2201/3236

    Abstract: An apparatus and method for watermarking that uses elemental images of an integrated image having three-dimensional information as a watermark are disclosed. The watermarking apparatus in accordance with an embodiment of the present invention includes i) a computational pickup unit, which picks up an elemental image watermark computationally by placing an object three-dimensionally, ii) an embedding process unit, which embeds into a two-dimensional image the elemental image watermark obtained by the computational pickup unit, iii) an extraction process unit, which extracts the elemental image watermark by receiving through a transmission channel the watermarked two-dimensional image embedded by the embedding process unit, and iv) a computational reconstruction unit, which computationally reconstructs the elemental image watermark extracted by the extraction process unit to a distance-based image.

    Abstract translation: 公开了一种使用具有三维信息的集成图像的元素图像作为水印的水印加密的装置和方法。 根据本发明实施例的电子水印装置包括：i）计算拾取单元，其通过三维放置对象来计算地拾取基本图像水印，ii）嵌入处理单元，其嵌入二维 对由计算机单元获得的元素图像水印进行成像，iii）提取处理单元，其通过传输通道接收由嵌入处理单元嵌入的水印二维图像提取基本图像水印，以及iv）计算重建 单元，其将由提取处理单元提取的元素图像水印计算重建为基于距离的图像。

    Apparatus and method for watermarking using elemental images of integrated image having three-dimensional information
    9.
    发明申请
    Apparatus and method for watermarking using elemental images of integrated image having three-dimensional information 失效
    使用具有三维信息的集成图像的元素图像进行水印加密的装置和方法

    公开(公告)号：US20080025564A1

    公开(公告)日：2008-01-31

    申请号：US11880224

    申请日：2007-07-19

    Applicant: Eun-Soo Kim ,  Dong-Choon Hwang ,  Dong-Hak Shin

    Inventor： Eun-Soo Kim ,  Dong-Choon Hwang ,  Dong-Hak Shin

    IPC: G06K9/00

    CPC classification number: H04N1/32154 ,  G06T1/0021 ,  G06T2201/0052 ,  H04N1/3217 ,  H04N13/261 ,  H04N2201/3236

    Abstract: An apparatus and method for watermarking that uses elemental images of an integrated image having three-dimensional information as a watermark are disclosed. The watermarking apparatus in accordance with an embodiment of the present invention includes i) a computational pickup unit, which picks up an elemental image watermark computationally by placing an object three-dimensionally, ii) an embedding process unit, which embeds into a two-dimensional image the elemental image watermark obtained by the computational pickup unit, iii) an extraction process unit, which extracts the elemental image watermark by receiving through a transmission channel the watermarked two-dimensional image embedded by the embedding process unit, and iv) a computational reconstruction unit, which computationally reconstructs the elemental image watermark extracted by the extraction process unit to a distance-based image.

    Abstract translation: 公开了一种使用具有三维信息的集成图像的元素图像作为水印的水印加密的装置和方法。 根据本发明实施例的电子水印装置包括：i）计算拾取单元，其通过三维放置对象来计算地拾取基本图像水印，ii）嵌入处理单元，其嵌入二维 对由计算机单元获得的元素图像水印进行成像，iii）提取处理单元，其通过传输通道接收由嵌入处理单元嵌入的水印二维图像提取基本图像水印，以及iv）计算重建 单元，其将由提取处理单元提取的元素图像水印计算重建为基于距离的图像。

    Plural bank semiconductor memory device with increased boosting voltage stability
    10.
    发明授权
    Plural bank semiconductor memory device with increased boosting voltage stability 失效
    多块半导体存储器件具有增加的升压稳定性

    公开(公告)号：US07307897B2

    公开(公告)日：2007-12-11

    申请号：US11267805

    申请日：2005-11-04

    Applicant: Dong-Hak Shin

    Inventor： Dong-Hak Shin

    IPC: G11C5/14

    CPC classification number: G11C11/417 ,  G11C5/145

    Abstract: A semiconductor memory device includes a memory cell array, and first and second boosting voltage generating portions. The first boosting voltage generating portion generates a first driving signal when the semiconductor device operates in an active mode and supplies a boosting voltage that is higher than a power supply voltage to an output terminal in response to the first driving signal. The second boosting voltage generating portion includes a first boosting voltage generator generating a second driving signal when a level of the boosting voltage of the output terminal is below a target level in the active mode and pumping the boosting voltage in response to the second driving signal and a second boosting voltage generator pumping the boosting voltage in response to the first driving signal when first memory cell array blocks are selected and pumping the boosting voltage in response to the second driving signal when second memory cell array blocks are selected.

    Abstract translation: 半导体存储器件包括存储单元阵列，以及第一和第二升压电压产生部分。 当半导体器件工作在有源模式时，第一升压电压产生部分产生第一驱动信号，并响应于第一驱动信号向输出端提供高于电源电压的升压电压。 第二升压电压产生部分包括第一升压电压发生器，当所述输出端子的升压电压的电平低于所述激活模式中的目标电平并且响应于所述第二驱动信号而泵浦所述升压电压时产生第二驱动信号;以及 当选择第一存储单元阵列块时，第二升压电压发生器响应于第一驱动信号而泵浦升压电压，并且当选择第二存储单元阵列块时响应于第二驱动信号来泵浦升压电压。

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