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    Dynamic random access memory with smart refresh scheduler
    1.
    发明授权
    Dynamic random access memory with smart refresh scheduler 有权
    具有智能刷新调度器的动态随机存取存储器

    公开(公告)号：US06954387B2

    公开(公告)日：2005-10-11

    申请号：US10604375

    申请日：2003-07-15

    申请人： Hoki Kim ,  Toshiaki Kirihata ,  David R. Hanson ,  Gregory J. Fredeman ,  John Golz

    发明人： Hoki Kim ,  Toshiaki Kirihata ,  David R. Hanson ,  Gregory J. Fredeman ,  John Golz

    IPC分类号： G11C11/406 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C2207/104

    摘要： In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.

    摘要翻译： 在包括多个存储体的DRAM中，对于每个存储体，存在分别向上/向下移位的标志位寄存器的一对分离的标志位寄存器。 每个组的比较器提供一个比较器输出。 每个存储体的仲裁器被连接以从该存储体的标志位寄存器和对于该存储体的比较器输出的比较器输出标志位向上信号和标志位降低信号。 仲裁器被连接以接收信号中的冲突并提供冲突信号。 一对标志位寄存器表示每个存储体的刷新状态，并指定准备进行刷新操作的存储体或阵列。

    Structure and method of making three finger folded field effect transistors having shared junctions
    2.
    发明授权
    Structure and method of making three finger folded field effect transistors having shared junctions 失效
    制造具有共同连接点的三指折叠场效应晶体管的结构和方法

    公开(公告)号：US06768143B1

    公开(公告)日：2004-07-27

    申请号：US10604913

    申请日：2003-08-26

    申请人： Gregory J. Fredeman ,  John W. Golz ,  David R. Hanson ,  Hoki Kim

    发明人： Gregory J. Fredeman ,  John W. Golz ,  David R. Hanson ,  Hoki Kim

    IPC分类号： H01L2710

    CPC分类号： H01L27/10897 ,  G11C11/4085

    摘要： An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.

    摘要翻译： 提供了包括场效应晶体管（FET）的集成电路，其中栅极导通器具有设置在衬底的交替的源极和漏极区域之间的偶数个指状物。 手指在图案上设置有在水平方向上具有长度的区域的区域，该区域等于长度乘以由奇数手指占据的垂直方向上的宽度。

    Low power manager for standby operation of a memory system
    3.
    发明授权
    Low power manager for standby operation of a memory system 有权
    低功耗管理器用于存储系统的待机操作

    公开(公告)号：US07023758B2

    公开(公告)日：2006-04-04

    申请号：US11205565

    申请日：2005-08-17

    申请人： David R. Hanson ,  Gregory J Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

    发明人： David R. Hanson ,  Gregory J Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

    IPC分类号： G11C7/00

    CPC分类号： G11C5/143 ,  G11C8/08

    摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

    摘要翻译： 存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线 司机。 具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

    DYNAMIC RANDOM ACCESS MEMORY WITH SMART REFRESH SCHEDULER
    4.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY WITH SMART REFRESH SCHEDULER 有权
    动态随机存取存储器与SMART REFRESH SCHEDULER

    公开(公告)号：US20050013185A1

    公开(公告)日：2005-01-20

    申请号：US10604375

    申请日：2003-07-15

    申请人： Hoki Kim ,  Toshiaki Kirihata ,  David Hanson ,  Gregory Fredeman ,  John Golz

    发明人： Hoki Kim ,  Toshiaki Kirihata ,  David Hanson ,  Gregory Fredeman ,  John Golz

    IPC分类号： G11C11/406 ,  G11C7/00

    CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C2207/104

    摘要： In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.

    摘要翻译： 在包括多个存储体的DRAM中，对于每个存储体，存在分别向上/向下移位的标志位寄存器的一对分离的标志位寄存器。 每个组的比较器提供一个比较器输出。 每个存储体的仲裁器被连接以从该存储体的标志位寄存器和对于该存储体的比较器输出的比较器输出标志位向上信号和标志位降低信号。 仲裁器被连接以接收信号中的冲突并提供冲突信号。 一对标志位寄存器表示每个存储体的刷新状态，并指定准备进行刷新操作的存储体或阵列。

    Low power manager for standby operation of memory system
    5.
    发明授权
    Low power manager for standby operation of memory system 有权
    低功耗管理器用于存储系统的待机操作

    公开(公告)号：US07046572B2

    公开(公告)日：2006-05-16

    申请号：US10250233

    申请日：2003-06-16

    申请人： David R. Hansen ,  Gregory J. Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

    发明人： David R. Hansen ,  Gregory J. Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

    IPC分类号： G11C7/00

    CPC分类号： G11C5/143 ,  G11C8/08

    摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

    摘要翻译： 存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线 司机。 具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

    SINGLE CYCLE REFRESH OF MULTI-PORT DYNAMIC RANDOM ACCESS MEMORY (DRAM)
    6.
    发明申请
    SINGLE CYCLE REFRESH OF MULTI-PORT DYNAMIC RANDOM ACCESS MEMORY (DRAM) 有权
    多端口动态随机存取存储器（DRAM）的单周期刷新

    公开(公告)号：US20060285411A1

    公开(公告)日：2006-12-21

    申请号：US11160273

    申请日：2005-06-16

    申请人： Hoki Kim ,  Toshiaki Kirihata

    发明人： Hoki Kim ,  Toshiaki Kirihata

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4097 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4094

    摘要： A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.

    摘要翻译： 具有与正常读取和写入操作交织的刷新周期的多端口DRAM通过推迟序列的写入部分直到下一个刷新周期来实现单周期刷新序列。 在单个时钟周期内，系统将存储的数据从刷新缓冲区写入存储器阵列中的一行，然后将数据从存储器阵列的一行读入缓冲区。

    Single cycle refresh of multi-port dynamic random access memory (DRAM)
    7.
    发明授权
    Single cycle refresh of multi-port dynamic random access memory (DRAM) 有权
    多端口动态随机存取存储器（DRAM）的单周期刷新

    公开(公告)号：US07145829B1

    公开(公告)日：2006-12-05

    申请号：US11160273

    申请日：2005-06-16

    申请人： Hoki Kim ,  Toshiaki Kirihata

    发明人： Hoki Kim ,  Toshiaki Kirihata

    IPC分类号： C11C7/00

    CPC分类号： G11C11/4097 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4094

    摘要： A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.

    摘要翻译： 具有与正常读取和写入操作交错的刷新周期的多端口DRAM通过推迟序列的写入部分直到下一个刷新周期来实现单周期刷新序列。 在单个时钟周期内，系统将存储的数据从刷新缓冲区写入存储器阵列中的一行，然后将数据从存储器阵列的一行读入缓冲区。

    Three Dimensional Twisted Bitline Architecture for Multi-port Memory
    8.
    发明申请
    Three Dimensional Twisted Bitline Architecture for Multi-port Memory 失效
    用于多端口存储器的三维扭转位线架构

    公开(公告)号：US20090103390A1

    公开(公告)日：2009-04-23

    申请号：US11875173

    申请日：2007-10-19

    申请人： Hoki Kim ,  Toshiaki Kirihata

    发明人： Hoki Kim ,  Toshiaki Kirihata

    IPC分类号： G11C8/00

    CPC分类号： G11C8/16 ,  G11C7/02 ,  G11C7/1075 ,  G11C7/18 ,  G11C11/412

    摘要： Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical position of each bit line pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.

    摘要翻译： 本发明的实施例提供了双重部分单元的存储器阵列及其设计结构。 存储器阵列具有一对扭曲的写位线和用于每列的一对扭转的读位线。 通过在列的每个部分中交替每个位线对的垂直位置来进行扭转，从而产生共模鼻子并且减小差模噪声。