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公开(公告)号：US20080164929A1
公开(公告)日：2008-07-10
申请号：US11908966
申请日：2006-03-15
IPC分类号： H03H11/26
CPC分类号： H03K5/13 , G06F9/3869 , H03K2005/00058 , H03K2005/00247
摘要： The electronic circuit contains a basic delay circuit (14). A delay is realized by activating the same basic delay circuit (14) a plurality of times in response to a single start signal before generating a response to that start signal. A control circuit (12) receives a start signal and an outputs a response. The control circuit (12) causes a series of signals to be passed through the delay circuit (14), the series starting at a time that is time-continuously triggered by the start signal. Each successive signal in the series starts after a preceding signal has emerged from the delay circuit (12) and the series being terminated after a controlled number of more than one signal has been passed. The control circuit (12) supplies the response upon termination of the series. In one embodiment the series is realized by means of a handshake sequencing circuit (120) that generates a series of successive handshake transactions.
摘要翻译： 电子电路包含基本延迟电路（14）。 通过在产生对该起始信号的响应之前响应于单个起始信号激活相同的基本延迟电路（14）来实现延迟。 控制电路（12）接收起始信号并输出响应。 控制电路（12）使一系列信号通过延迟电路（14），该串联信号从由起始信号时间连续触发的时间开始。 在从延迟电路（12）出现先前的信号之后，串联中的每个连续信号开始，并且在经过多个信号的受控数量之后，串联被终止。 控制电路（12）在串联终止时提供响应。 在一个实施例中，该系列通过产生一系列连续握手事务的握手排序电路（120）来实现。
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公开(公告)号：US07519759B2
公开(公告)日：2009-04-14
申请号：US10542906
申请日：2004-01-14
CPC分类号： G06F9/3869 , H04L7/02
摘要： Pipeline synchronization device for transferring data between clocked devices having different clock frequencies. The Pipeline synchronization device comprises a mousetrap buffer for exchanging data with one of said external devices said mousetrap buffer having a signalling output for coordinating the data exchange with the external device. The pipeline synchronization device comprises further a synchronizer adapted to synchronizing the change in a signalling output with the clock of the external device.
摘要翻译： 用于在具有不同时钟频率的时钟设备之间传送数据的流水线同步装置。 管道同步装置包括用于与所述外部设备之一交换数据的捕鼠器缓冲器，所述捕鼠器缓冲器具有用于协调与外部设备的数据交换的信令输出。 流水线同步装置还包括一个同步器，该同步器适于使信令输出的变化与外部设备的时钟同步。
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公开(公告)号：US07185220B2
公开(公告)日：2007-02-27
申请号：US10500520
申请日：2002-12-06
CPC分类号： G06F1/08
摘要： A locally synchronous circuit module has a delay circuit having and input and output coupled to a clock input. The delay circuit provides a delay which when incorporated in a clock oscillator ensures a clock period that is at least as long as needed to transfer information between the storage elements. A handshake circuit is provided for generating handshake signals for timing information transfer between the locally synchronous circuit module and a further circuit. The handshake circuit comprises the delay circuit, so that at least part of the handshake signals during a handshake transaction are timed by traveling through the delay circuit and are applied to the clock input to clock the locally synchronous circuit module.
摘要翻译： 本地同步电路模块具有延迟电路，其具有耦合到时钟输入的输入和输出。 延迟电路提供了延迟，当并入时钟振荡器中时，可以确保在存储元件之间传送信息所需的时钟周期至少等同于长度。 提供握手电路，用于产生用于本地同步电路模块和另一电路之间的定时信息传送的握手信号。 握手电路包括延迟电路，使得在握手事务期间的握手信号的至少一部分通过行进延迟电路来计时，并被施加到时钟输入以对本地同步电路模块进行时钟。
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公开(公告)号：US06614290B2
公开(公告)日：2003-09-02
申请号：US10067044
申请日：2002-02-04
申请人： Patrick Willem Hubert Heuts , Jozef Laurentius Wilhelmus Kessels , Adrianus Marinus Gerardus Peeters
发明人： Patrick Willem Hubert Heuts , Jozef Laurentius Wilhelmus Kessels , Adrianus Marinus Gerardus Peeters
IPC分类号： G06F1100
CPC分类号： G01R31/318536
摘要： An integrated circuit according to the invention comprises at least a first and a second circuit (1, 2 resp.) and a first and a second signal path (10-20 and 11-21 resp.) between the first and the second circuit. The first and the second signal path each comprise a selection element (30) which has a first input (30a, 31a) coupled to the first circuit (1), and a second input (30b, 31b). The selection element (30) has an output (30c, 31c) coupled to the second circuit (2). The second input (31b) of the selection element (31) of the second signal path (11-21) is coupled to a memory element (41). The output (40a) of the selection element (30) of the first signal path (10-20) is coupled to an input (40a) of the memory element (40).
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公开(公告)号：US20120303921A1
公开(公告)日：2012-11-29
申请号：US13481914
申请日：2012-05-28
IPC分类号： G06F12/00
CPC分类号： G06F13/1642 , G06F13/1673 , Y02D10/14
摘要： A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted.
摘要翻译： 数据处理装置包含多个处理电路，每个处理电路在其自己的周期时钟信号的控制下操作，使得时钟信号可以具有不同的频率和/或可以是自主的。 多个处理电路各自具有用于输出存储器访问请求的输出，其存储在由特定处理器的时钟信号定义的有效期间隔的输出处。 复用电路将访问请求复用到存储器。 存储器需要最小的存储器重复周期，才能在接受前面的访问请求之后接受访问请求。 处理电路的时钟周期比最小存储器重复周期长。 定时电路选择接受来自第一数据处理电路的每个特定访问请求的接收时间点。
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公开(公告)号：US07831853B2
公开(公告)日：2010-11-09
申请号：US10591546
申请日：2005-02-25
摘要： A circuit is described comprising a first (10) and a second circuit module (20) and a synchronization module (30). The first and the second module are mutually asynchronous, and are coupled by the synchronization module. The synchronization module (30) comprises: a transfer register (31) for storing data which is communicated between the two circuit modules, a control circuit (32) for controlling the register in response to a respective timing signal (St1, St2) from the first and the second circuit module, the control circuit comprising a control chain for generating a control signal (CR) for the transfer register (31). The control chain includes at least: a repeater (34) for inducing changes in the value of the control signal, at least one edge sensitive element (35) for delaying a change in the signal value until a transition in a selected one of the timing signals is detected.
摘要翻译： 描述了包括第一（10）和第二电路模块（20）和同步模块（30）的电路。 第一和第二模块是相互异步的，并且由同步模块耦合。 同步模块（30）包括：传输寄存器（31），用于存储在两个电路模块之间通信的数据;控制电路（32），用于响应于来自所述两个电路模块的相应定时信号（St1，St2）控制寄存器 第一和第二电路模块，所述控制电路包括用于产生所述传送寄存器（31）的控制信号（CR）的控制链。 所述控制链至少包括：用于引起所述控制信号的值的改变的中继器（34），用于延迟所述信号值的变化的至少一个边缘敏感元件（35），直到所选择的一个定时 检测到信号。
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公开(公告)号：US07487300B2
公开(公告)日：2009-02-03
申请号：US10560450
申请日：2004-06-09
IPC分类号： G06F13/14
CPC分类号： G06F13/1642 , G06F13/1673 , Y02D10/14
摘要： A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted. The time point at which the particular request is accepted is always within the validity duration interval in which the particular access request is made. The timing circuit varies the position of the acceptance time points within the validity duration intervals, so that the position is delayed to make room for previously accepting an access request from another processor. The position is subsequently moved back toward a start of the validity duration interval in successive steps during application of successive access requests from the first data processing circuit.
摘要翻译： 数据处理装置包含多个处理电路，每个处理电路在其自己的周期时钟信号的控制下操作，使得时钟信号可以具有不同的频率和/或可以是自主的。 多个处理电路各自具有用于输出存储器访问请求的输出，其存储在由特定处理器的时钟信号定义的有效期间隔的输出处。 复用电路将访问请求复用到存储器。 存储器需要最小的存储器重复周期，才能在接受前面的访问请求之后接受访问请求。 处理电路的时钟周期比最小存储器重复周期长。 定时电路选择接受来自第一数据处理电路的每个特定访问请求的接收时间点。 特定请求被接受的时间点总是在进行特定访问请求的有效期间隔内。 定时电路在有效持续时间间隔内改变接受时间点的位置，使得位置被延迟以便先前接受来自另一处理器的访问请求的空间。 随后在应用来自第一数据处理电路的连续访问请求期间，该位置在连续的步骤中向着有效持续时间间隔的开始移回。
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公开(公告)号：US08473706B2
公开(公告)日：2013-06-25
申请号：US13481914
申请日：2012-05-28
IPC分类号： G06F12/00
CPC分类号： G06F13/1642 , G06F13/1673 , Y02D10/14
摘要： A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted.
摘要翻译： 数据处理装置包含多个处理电路，每个处理电路在其自己的周期时钟信号的控制下操作，使得时钟信号可以具有不同的频率和/或可以是自主的。 多个处理电路各自具有用于输出存储器访问请求的输出，其存储在由特定处理器的时钟信号定义的有效期间隔的输出处。 复用电路将访问请求复用到存储器。 存储器需要最小的存储器重复周期，才能在接受前面的访问请求之后接受访问请求。 处理电路的时钟周期比最小存储器重复周期长。 定时电路选择接受来自第一数据处理电路的每个特定访问请求的接收时间点。
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公开(公告)号：US06827278B1
公开(公告)日：2004-12-07
申请号：US09555306
申请日：2000-10-06
申请人： Volker Timm , Ralf Malzahn , Wolfgang Eber , Dominik Berger , Jozef Laurentius Wilhelmus Kessels , Torsten Kramer
发明人： Volker Timm , Ralf Malzahn , Wolfgang Eber , Dominik Berger , Jozef Laurentius Wilhelmus Kessels , Torsten Kramer
IPC分类号： G06K1906
CPC分类号： G06K19/07769 , G06K19/07 , G06K19/0701 , G06K19/073
摘要： A data carrier is disclosed. The data carrier includes a data processing unit and at least one contactless interface via which the data processing unit can be coupled to a read/write apparatus in order to exchange data signals and to take up electrical energy for the operation of the data processing unit; the data processing unit is constructed at least mainly while using at least substantially asynchronously operating logic components (asynchronous logic). The data carrier according to the invention, such as a chip card, makes optimum use of the energy applied thereto and is at the same time protected against the tapping of the signal processing steps to be executed therein.
摘要翻译： 公开了数据载体。 数据载体包括数据处理单元和至少一个非接触式接口，通过该接口，数据处理单元可耦合到读/写设备，以便交换数据信号并占用用于数据处理单元操作的电能; 数据处理单元至少主要构造在使用至少基本上异步操作的逻辑组件（异步逻辑）的同时。 根据本发明的数据载体，例如芯片卡，可以最佳地利用施加到其上的能量，同时可以防止在其中执行的信号处理步骤的窃听。
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