公开(公告)号：US20060255399A1

公开(公告)日：2006-11-16

申请号：US11354076

申请日：2006-02-15

申请人： Ju-Hyung Kim ,  Jeong-Hee Han ,  Chung-Woo Kim ,  Yo-Sep Min ,  Moon-Kyung Kim ,  Youn-Seok Jeong

发明人： Ju-Hyung Kim ,  Jeong-Hee Han ,  Chung-Woo Kim ,  Yo-Sep Min ,  Moon-Kyung Kim ,  Youn-Seok Jeong

IPC分类号： H01L29/792

CPC分类号： H01L29/7881 ,  H01L29/4232 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/792

摘要： Provided is a nonvolatile memory device which includes a tunneling insulating film formed on a semiconductor substrate, a storage node formed on the tunneling insulating film, a blocking insulating film formed on the storage node, and a control gate electrode formed on the blocking insulating film. The storage node includes at least two trapping films having different trap densities, and the blocking insulating film has a dielectric constant greater than that of the silicon oxide film.

摘要翻译： 提供了一种非易失性存储器件，其包括形成在半导体衬底上的隧道绝缘膜，形成在隧道绝缘膜上的存储节点，形成在存储节点上的阻挡绝缘膜，以及形成在阻挡绝缘膜上的控制栅电极。 存储节点包括具有不同陷阱密度的至少两个俘获膜，并且阻挡绝缘膜的介电常数大于氧化硅膜的介电常数。

公开(公告)号：US20060186462A1

公开(公告)日：2006-08-24

申请号：US11357329

申请日：2006-02-21

申请人： Jeong-Hee Han ,  Ju-Hyung Kim ,  Chung-Woo Kim ,  Sang-Hun Jeon ,  Youn-Seok Jeong ,  Seung-Hyun Lee

发明人： Jeong-Hee Han ,  Ju-Hyung Kim ,  Chung-Woo Kim ,  Sang-Hun Jeon ,  Youn-Seok Jeong ,  Seung-Hyun Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L29/513 ,  H01L29/792

摘要： Provided are example embodiments of fabrication methods and resulting structures suitable for use in nonvolatile memory devices formed on semiconductor substrates. The example embodiments of the gate structures include a first insulating film formed on the semiconductor substrate, a storage node formed on the first insulating film for storing charges, a second insulating film formed on the storage node, a third insulating film formed on the second insulating film, and a gate electrode formed on the third insulating film. The insulating films are selected whereby the dielectric constant of one or both of the second and third insulating films is greater than the dielectric constant of the first insulating film.

摘要翻译： 提供了适用于形成在半导体衬底上的非易失性存储器件中的制造方法和结果结构的示例性实施例。 栅极结构的示例实施例包括形成在半导体衬底上的第一绝缘膜，形成在用于存储电荷的第一绝缘膜上的存储节点，形成在存储节点上的第二绝缘膜，形成在第二绝缘层上的第三绝缘膜 膜和形成在第三绝缘膜上的栅电极。 选择绝缘膜，由此第二和第三绝缘膜中的一个或两个的介电常数大于第一绝缘膜的介电常数。

公开(公告)号：US07456468B2

公开(公告)日：2008-11-25

申请号：US11335431

申请日：2006-01-18

申请人： Sang-Hun Jeon ,  Sung-Kyu Choi ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Ho Park ,  Jeong-Hee Han ,  Sang-Moo Choi

发明人： Sang-Hun Jeon ,  Sung-Kyu Choi ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Ho Park ,  Jeong-Hee Han ,  Sang-Moo Choi

IPC分类号： H01L29/792

CPC分类号： H01L21/02148 ,  H01L21/02156 ,  H01L21/02159 ,  H01L21/28282 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/792

摘要： A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected from the group consisting of Hf, Zr, Y, and Ln, and a gate electrode layer disposed on the insulating layer.

摘要翻译： 半导体存储器件，第一掺杂剂区域和第二掺杂剂区域，设置在半导体衬底中的第一掺杂区域和第二掺杂剂区域，与第一掺杂区域和第二掺杂剂区域接触设置的绝缘层，绝缘层包括 选自Hf，Zr，Y和Ln的材料以及设置在绝缘层上的栅电极层。

公开(公告)号：US20080128757A1

公开(公告)日：2008-06-05

申请号：US11999135

申请日：2007-12-04

申请人： Soo-Doo Chae ,  Chung-Woo Kim ,  Chan-Jin Park ,  Jeong-Hee Han ,  Byung-Gook Park ,  Il-Han Park

发明人： Soo-Doo Chae ,  Chung-Woo Kim ,  Chan-Jin Park ,  Jeong-Hee Han ,  Byung-Gook Park ,  Il-Han Park

IPC分类号： G11C11/407 ,  H01L29/788

CPC分类号： H01L27/115 ,  G11C16/0416 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash memory device can include a semiconductor pin protruding from a semiconductor substrate of a first conductive type to extend in one direction, a first doped layer and a second doped layer provided to an upper portion and a lower portion of the semiconductor pin, respectively, to be vertically spaced apart from each other, the first and second doped layers having a second conductive type, and a plurality of word lines extending over a top and a sidewall of the semiconductor pin to intersect the direction. The word lines overlap the first doped layer and the second doped layer to have vertical channels.

摘要翻译： 闪速存储器件可以包括从第一导电类型的半导体衬底突出以在一个方向上延伸的半导体引脚，分别设置到半导体引脚的上部和下部的第一掺杂层和第二掺杂层， 彼此垂直间隔开，第一和第二掺杂层具有第二导电类型，并且多个字线在半导体引脚的顶部和侧壁上延伸以与该方向相交。 字线与第一掺杂层和第二掺杂层重叠以具有垂直沟道。

公开(公告)号：US07646041B2

公开(公告)日：2010-01-12

申请号：US11999135

申请日：2007-12-04

申请人： Soo-Doo Chae ,  Chung-Woo Kim ,  Chan-Jin Park ,  Jeong-Hee Han ,  Byung-Gook Park ,  Il-Han Park

发明人： Soo-Doo Chae ,  Chung-Woo Kim ,  Chan-Jin Park ,  Jeong-Hee Han ,  Byung-Gook Park ,  Il-Han Park

IPC分类号： H01L27/108

CPC分类号： H01L27/115 ,  G11C16/0416 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash memory device can include a semiconductor fin protruding from a semiconductor substrate of a first conductive type to extend in one direction, a first doped layer and a second doped layer provided to an upper portion and a lower portion of the semiconductor fin, respectively, to be vertically spaced apart from each other, the first and second doped layers having a second conductive type, and a plurality of word lines extending over a top and a sidewall of the semiconductor fin to intersect the direction. The word lines overlap the first doped layer and the second doped layer to have vertical channels.

摘要翻译： 闪存器件可以包括从第一导电类型的半导体衬底突出以在一个方向上延伸的半导体鳍片，分别设置在半导体鳍片的上部和下部的第一掺杂层和第二掺杂层， 彼此垂直间隔开，第一和第二掺杂层具有第二导电类型，并且多个字线在半导体鳍片的顶部和侧壁上延伸以与该方向相交。 字线与第一掺杂层和第二掺杂层重叠以具有垂直沟道。

公开(公告)号：US20060157754A1

公开(公告)日：2006-07-20

申请号：US11335431

申请日：2006-01-18

申请人： Sang-Hun Jeon ,  Sung-Kyu Choi ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Ho Park ,  Jeong-Hee Han ,  Sang-Moo Choi

发明人： Sang-Hun Jeon ,  Sung-Kyu Choi ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Ho Park ,  Jeong-Hee Han ,  Sang-Moo Choi

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L21/02148 ,  H01L21/02156 ,  H01L21/02159 ,  H01L21/28282 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/792

摘要： A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected from the group consisting of Hf, Zr, Y, and Ln, and a gate electrode layer disposed on the insulating layer.

摘要翻译： 半导体存储器件，第一掺杂剂区域和第二掺杂剂区域，设置在半导体衬底中的第一掺杂区域和第二掺杂剂区域，与第一掺杂区域和第二掺杂剂区域接触设置的绝缘层，绝缘层包括 选自Hf，Zr，Y和Ln的材料以及设置在绝缘层上的栅电极层。

公开(公告)号：US07432554B2

公开(公告)日：2008-10-07

申请号：US11305394

申请日：2005-12-16

申请人： Moon-Kyung Kim ,  Jo-Won Lee ,  Yoon-Dong Park ,  Chung-Woo Kim

发明人： Moon-Kyung Kim ,  Jo-Won Lee ,  Yoon-Dong Park ,  Chung-Woo Kim

IPC分类号： H01L27/08

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A complementary metal oxide semiconductor (CMOS) thin film transistor including a common gate, a logic device including the CMOS thin film transistor, and a method of manufacturing the CMOS thin film transistor are provided. In one embodiment, the CMOS thin film transistor includes a base substrate and a semiconductor layer formed on the base substrate. A PMOS transistor and an NMOS transistor are formed on a single semiconductor layer to intersect each other, and a common gate is formed on the intersection area. In addition, a Schottky barrier inducing material layer is formed on a source and a drain of the PMOS transistor.

摘要翻译： 提供了包括公共栅极的互补金属氧化物半导体（CMOS）薄膜晶体管，包括CMOS薄膜晶体管的逻辑器件和制造CMOS薄膜晶体管的方法。 在一个实施例中，CMOS薄膜晶体管包括基底基板和形成在基底基板上的半导体层。 PMOS晶体管和NMOS晶体管形成在单个半导体层上以彼此相交，并且在交叉区域上形成公共栅极。 此外，在PMOS晶体管的源极和漏极上形成肖特基势垒诱导材料层。

公开(公告)号：US20060131653A1

公开(公告)日：2006-06-22

申请号：US11305394

申请日：2005-12-16

申请人： Moon-Kyung Kim ,  Jo-Won Lee ,  Yoon-Dong Park ,  Chung-Woo Kim

发明人： Moon-Kyung Kim ,  Jo-Won Lee ,  Yoon-Dong Park ,  Chung-Woo Kim

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A complementary metal oxide semiconductor (CMOS) thin film transistor including a common gate, a logic device including the CMOS thin film transistor, and a method of manufacturing the CMOS thin film transistor are provided. In one embodiment, the CMOS thin film transistor includes a base substrate and a semiconductor layer formed on the base substrate. A PMOS transistor and an NMOS transistor are formed on a single semiconductor layer to intersect each other, and a common gate is formed on the intersection area. In addition, a Schottky barrier inducing material layer is formed on a source and a drain of the PMOS transistor.

摘要翻译： 提供了包括公共栅极的互补金属氧化物半导体（CMOS）薄膜晶体管，包括CMOS薄膜晶体管的逻辑器件和制造CMOS薄膜晶体管的方法。 在一个实施例中，CMOS薄膜晶体管包括基底基板和形成在基底基板上的半导体层。 PMOS晶体管和NMOS晶体管形成在单个半导体层上以彼此相交，并且在交叉区域上形成公共栅极。 此外，在PMOS晶体管的源极和漏极上形成肖特基势垒诱导材料层。

公开(公告)号：US07670916B2

公开(公告)日：2010-03-02

申请号：US12417432

申请日：2009-04-02

申请人： Sang-Hun Jeon ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Kweon Baek ,  Sang-Moo Choi

发明人： Sang-Hun Jeon ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Kweon Baek ,  Sang-Moo Choi

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/0843 ,  H01L29/167 ,  H01L29/792

摘要： A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.

摘要翻译： 半导体存储器件包括在半导体衬底中的第一掺杂区域和第二掺杂剂区域，掺杂有Sb，Ga和Bi组成的组的第一掺杂区域和第二掺杂剂区域。 半导体存储器件包括与第一掺杂剂区域和第二掺杂剂区域接触设置的绝缘层和与绝缘层接触设置的栅极电极层。

公开(公告)号：US07531865B2

公开(公告)日：2009-05-12

申请号：US11333959

申请日：2006-01-17

申请人： Sang-Hun Jeon ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Kweon Baek ,  Sang-Moo Choi

发明人： Sang-Hun Jeon ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Kweon Baek ,  Sang-Moo Choi

IPC分类号： H01L29/788

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/0843 ,  H01L29/167 ,  H01L29/792

摘要： A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.

摘要翻译： 半导体存储器件包括在半导体衬底中的第一掺杂区域和第二掺杂剂区域，掺杂有Sb，Ga和Bi组成的组的第一掺杂区域和第二掺杂剂区域。 半导体存储器件包括与第一掺杂剂区域和第二掺杂剂区域接触设置的绝缘层和与绝缘层接触设置的栅极电极层。