公开(公告)号：US07670916B2

公开(公告)日：2010-03-02

申请号：US12417432

申请日：2009-04-02

申请人： Sang-Hun Jeon ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Kweon Baek ,  Sang-Moo Choi

发明人： Sang-Hun Jeon ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Kweon Baek ,  Sang-Moo Choi

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/0843 ,  H01L29/167 ,  H01L29/792

摘要： A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.

摘要翻译： 半导体存储器件包括在半导体衬底中的第一掺杂区域和第二掺杂剂区域，掺杂有Sb，Ga和Bi组成的组的第一掺杂区域和第二掺杂剂区域。 半导体存储器件包括与第一掺杂剂区域和第二掺杂剂区域接触设置的绝缘层和与绝缘层接触设置的栅极电极层。

公开(公告)号：US07531865B2

公开(公告)日：2009-05-12

申请号：US11333959

申请日：2006-01-17

申请人： Sang-Hun Jeon ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Kweon Baek ,  Sang-Moo Choi

发明人： Sang-Hun Jeon ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Kweon Baek ,  Sang-Moo Choi

IPC分类号： H01L29/788

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/0843 ,  H01L29/167 ,  H01L29/792

摘要： A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.

摘要翻译： 半导体存储器件包括在半导体衬底中的第一掺杂区域和第二掺杂剂区域，掺杂有Sb，Ga和Bi组成的组的第一掺杂区域和第二掺杂剂区域。 半导体存储器件包括与第一掺杂剂区域和第二掺杂剂区域接触设置的绝缘层和与绝缘层接触设置的栅极电极层。

公开(公告)号：US20060157777A1

公开(公告)日：2006-07-20

申请号：US11333959

申请日：2006-01-17

申请人： Sang-Hun Jeon ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Kweon Baek ,  Sang-Moo Choi

发明人： Sang-Hun Jeon ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Kweon Baek ,  Sang-Moo Choi

IPC分类号： H01L29/792

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/0843 ,  H01L29/167 ,  H01L29/792

摘要： A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.

摘要翻译： 半导体存储器件包括在半导体衬底中的第一掺杂区域和第二掺杂剂区域，掺杂有Sb，Ga和Bi组成的组的第一掺杂区域和第二掺杂剂区域。 半导体存储器件包括与第一掺杂剂区域和第二掺杂剂区域接触设置的绝缘层和与绝缘层接触设置的栅极电极层。

公开(公告)号：US07456468B2

公开(公告)日：2008-11-25

申请号：US11335431

申请日：2006-01-18

申请人： Sang-Hun Jeon ,  Sung-Kyu Choi ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Ho Park ,  Jeong-Hee Han ,  Sang-Moo Choi

发明人： Sang-Hun Jeon ,  Sung-Kyu Choi ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Ho Park ,  Jeong-Hee Han ,  Sang-Moo Choi

IPC分类号： H01L29/792

CPC分类号： H01L21/02148 ,  H01L21/02156 ,  H01L21/02159 ,  H01L21/28282 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/792

摘要： A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected from the group consisting of Hf, Zr, Y, and Ln, and a gate electrode layer disposed on the insulating layer.

摘要翻译： 半导体存储器件，第一掺杂剂区域和第二掺杂剂区域，设置在半导体衬底中的第一掺杂区域和第二掺杂剂区域，与第一掺杂区域和第二掺杂剂区域接触设置的绝缘层，绝缘层包括 选自Hf，Zr，Y和Ln的材料以及设置在绝缘层上的栅电极层。

公开(公告)号：US20060157754A1

公开(公告)日：2006-07-20

申请号：US11335431

申请日：2006-01-18

申请人： Sang-Hun Jeon ,  Sung-Kyu Choi ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Ho Park ,  Jeong-Hee Han ,  Sang-Moo Choi

发明人： Sang-Hun Jeon ,  Sung-Kyu Choi ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sung-Ho Park ,  Jeong-Hee Han ,  Sang-Moo Choi

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L21/02148 ,  H01L21/02156 ,  H01L21/02159 ,  H01L21/28282 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/792

摘要： A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected from the group consisting of Hf, Zr, Y, and Ln, and a gate electrode layer disposed on the insulating layer.

摘要翻译： 半导体存储器件，第一掺杂剂区域和第二掺杂剂区域，设置在半导体衬底中的第一掺杂区域和第二掺杂剂区域，与第一掺杂区域和第二掺杂剂区域接触设置的绝缘层，绝缘层包括 选自Hf，Zr，Y和Ln的材料以及设置在绝缘层上的栅电极层。

公开(公告)号：US20060192246A1

公开(公告)日：2006-08-31

申请号：US11365114

申请日：2006-02-28

申请人： Sang-Hun Jeon ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sang-Moo Choi

发明人： Sang-Hun Jeon ,  Chung-Woo Kim ,  Hyun-Sang Hwang ,  Sang-Moo Choi

IPC分类号： H01L29/788 ,  H01L29/76

CPC分类号： B82Y10/00 ,  H01L29/40117 ,  H01L29/42332 ,  H01L29/792

摘要： In one embodiment, a memory device includes a gate structure comprising a metal nitride material in a charge storing layer on a semiconductor substrate. The gate structure is disposed between a first dopant region and a second dopant region formed on the semiconductor substrate. The metal nitride material is structured to function as a trap site for trapping a charge.

摘要翻译： 在一个实施例中，存储器件包括在半导体衬底上的电荷存储层中包括金属氮化物材料的栅极结构。 栅极结构设置在形成在半导体衬底上的第一掺杂区域和第二掺杂区域之间。 金属氮化物材料被构造成用作捕获电荷的陷阱位置。

公开(公告)号：US20080166890A1

公开(公告)日：2008-07-10

申请号：US11885834

申请日：2006-03-08

申请人： Hyun-Sang Hwang

发明人： Hyun-Sang Hwang

IPC分类号： H01L21/02

CPC分类号： H01L29/517 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3003 ,  H01L29/4966

摘要： The present invention relates to a high pressure hydrogen annealing method for MOSFET semiconductor device, and more particularly, to effectively remove a supersaturated hydrogen on a high-k insulating layer treated by a high pressure hydrogen annealing so that the reliability of a device is improved. In other words, in order to decrease an interfacial charge, it is required to perform a high density and a high pressure hydrogen annealing. In this case, a hydrogen is included at an interface and a bulk of a high-k insulating layer, resulting in improving the initial operational characteristics of a device by passivating interfacial charge existing at an interface, but deteriorating the reliability of a device due to the hydrogen remaining in the insulating bulk. Therefore, in the present invention, a high pressure hydrogen annealing is performed and the subsequent annealing is performed under an inert gas atmosphere for a long time to effectively remove hydrogen molecules remaining at the bulk.

摘要翻译： 本发明涉及一种用于MOSFET半导体器件的高压氢退火方法，更具体地说，涉及通过高压氢退火处理的高k绝缘层上的过饱和氢的有效去除，从而提高器件的可靠性。 换句话说，为了降低界面电荷，需要进行高密度和高压氢退火。 在这种情况下，氢被包含在高k绝缘层的界面和体积上，从而通过钝化界面处存在的界面电荷来改善器件的初始操作特性，但是由于 残留在绝缘体中的氢。 因此，在本发明中，进行高压氢退火，并且在惰性气体气氛下长时间进行随后的退火以有效地除去在本体上残留的氢分子。

公开(公告)号：US09231198B2

公开(公告)日：2016-01-05

申请号：US13120547

申请日：2009-09-22

申请人： Hyun-Sang Hwang ,  Myeong-Bum Pyun

发明人： Hyun-Sang Hwang ,  Myeong-Bum Pyun

IPC分类号： H01L45/00

CPC分类号： H01L45/085 ,  G11C2213/35 ,  H01L45/1233 ,  H01L45/149 ,  H01L45/1625 ,  H01L45/1683

摘要： Disclosed are a resistance-variable memory device including a carbide-based solid electrolyte membrane that has stable memory at a high temperature and a manufacturing method thereof. The resistance-variable memory device includes: a lower electrode, the carbide-based solid electrolyte membrane arranged on the lower electrode, and an upper electrode arranged on the solid electrolyte membrane. In addition, the method for manufacturing the resistance-variable memory device comprises: a step for forming the lower electrode on a substrate, a step for forming the carbide-based solid electrolyte membrane on the lower electrode, and a step for forming the upper electrode on the solid electrolyte membrane.

摘要翻译： 公开了一种包括在高温下具有稳定记忆的碳化物基固体电解质膜的电阻可变存储器件及其制造方法。 电阻可变存储装置包括：下电极，布置在下电极上的碳化物系固体电解质膜和布置在固体电解质膜上的上电极。 另外，电阻可变存储器件的制造方法包括：在基板上形成下部电极的步骤，在下部电极上形成碳化物系固体电解质膜的工序和形成上部电极的工序 在固体电解质膜上。

公开(公告)号：US08546861B2

公开(公告)日：2013-10-01

申请号：US13254690

申请日：2009-08-28

申请人： Hyun-Sang Hwang

发明人： Hyun-Sang Hwang

IPC分类号： H01L27/108

CPC分类号： H01L27/2436 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/18 ,  G11C2213/71 ,  G11C2213/78 ,  H01L27/249 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： Provided are a resistance change memory device with a three-dimensional structure, a resistance change memory device array, an electronic product, and a manufacturing method therefor. The device array includes a plurality of first directional data lines which are arranged on a substrate in parallel. A conductive pillar is positioned between sidewalls of the first directional data lines, which face each other. A resistance change material film is positioned between the sidewall of the conductive pillar and the sidewall of the data lines that are adjacent to the sidewall of the conductive pillar.

摘要翻译： 提供具有三维结构的电阻变化存储器件，电阻变化存储器件阵列，电子产品及其制造方法。 器件阵列包括并行布置在衬底上的多个第一方向数据线。 导电柱位于彼此面对的第一方向数据线的侧壁之间。 电阻变化材料膜位于导电柱的侧壁和与导电柱的侧壁相邻的数据线的侧壁之间。

公开(公告)号：US07528039B2

公开(公告)日：2009-05-05

申请号：US12021181

申请日：2008-01-28

申请人： Hyun-Sang Hwang ,  Ho-Kyung Park ,  Man Jang ,  Min-Seok Jo

发明人： Hyun-Sang Hwang ,  Ho-Kyung Park ,  Man Jang ,  Min-Seok Jo

IPC分类号： H01L21/336

CPC分类号： H01L21/28282

摘要： A method of fabricating a flash memory is provided. The method includes forming a tunneling insulating film, a charge storage film, and a blocking insulating film on a semiconductor substrate; performing High Temperature (HT) anneal for the resultant semiconductor substrate; and performing Low Temperature (LT) wet vapor anneal for the resultant semiconductor substrate.

摘要翻译： 提供一种制造闪速存储器的方法。 该方法包括在半导体衬底上形成隧道绝缘膜，电荷存储膜和阻挡绝缘膜; 对所得半导体衬底进行高温（HT）退火; 并对所得的半导体衬底进行低温（LT）湿蒸气退火。