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    PROCESS METHOD TO FABRICATE CMOS CIRCUITS WITH DUAL STRESS CONTACT ETCH-STOP LINER LAYERS
    1.
    发明申请
    PROCESS METHOD TO FABRICATE CMOS CIRCUITS WITH DUAL STRESS CONTACT ETCH-STOP LINER LAYERS 审中-公开
    具有双应力接触蚀刻层的CMOS电路的工艺方法

    公开(公告)号：US20090020791A1

    公开(公告)日：2009-01-22

    申请号：US11778321

    申请日：2007-07-16

    申请人： Shaofeng Yu ,  Juanita DeLoach ,  Brian A. Smith ,  Yaw S. Obeng ,  Scott Gregory Bushman

    发明人： Shaofeng Yu ,  Juanita DeLoach ,  Brian A. Smith ,  Yaw S. Obeng ,  Scott Gregory Bushman

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L29/7843

    摘要： Exemplary embodiments provide IC CMOS devices having dual stress layers and methods for their manufacture using a buffer layer stack between the two types of the stress layers. The buffer layer stack can include multiple buffer layers formed between a first type stress layer (e.g., a tensile stress layer) and a second type stress layer (e.g., a compressive stress layer) during the CMOS fabrication. Specifically, the buffer layer stack can be formed after the etching process of the first type stress layer but prior to the etching process of the second type stress layer, and thus to protect the etched first type stress layer during the subsequent etching process of the overlaid second type stress layer. In addition, a portion of the buffer layer stack can be formed between, for example, the compressive stress layer and the underlying PMOS device to enhance their adhesion.

    摘要翻译： 示例性实施例提供了具有双应力层的IC CMOS器件及其制造方法，使用两种类型的应力层之间的缓冲层堆叠。 缓冲层堆叠可以包括在CMOS制造期间在第一类型应力层（例如，拉伸应力层）和第二类型应力层（例如，压应力层）之间形成的多个缓冲层。 具体地说，缓冲层堆叠可以在第一类应力层的蚀刻工艺之后但是在第二种应力层的蚀刻工艺之前形成，从而在重叠的随后的蚀刻工艺期间保护蚀刻的第一类型应力层 第二类应力层。 此外，缓冲层堆叠的一部分可以形成在例如压应力层和下面的PMOS器件之间，以增强其粘附性。

    In situ hardmask pullback using an in situ plasma resist trim process
    2.
    发明授权
    In situ hardmask pullback using an in situ plasma resist trim process 有权
    使用原位等离子体抗蚀剂修整工艺的原位硬掩模拉回

    公开(公告)号：US07320927B2

    公开(公告)日：2008-01-22

    申请号：US10689177

    申请日：2003-10-20

    申请人： Juanita DeLoach ,  Brian A. Smith

    发明人： Juanita DeLoach ,  Brian A. Smith

    IPC分类号： H01L21/762

    CPC分类号： H01L21/823878 ,  H01L21/76232

    摘要： The present invention provides a process of manufacturing an isolation structure for use in a semiconductor device. The process includes forming an opening in a substrate through a patterned photoresist layer 225 and a hardmask layer 215 located over the substrate 205 with plasma, trimming the photoresist layer 225 with a plasma to create an exposed portion 215a of the hardmask layer 215, removing the exposed portion 215a with a plasma to create a trench guide opening 227, and creating a trench 230 through the trench guide opening 227 with a plasma.

    摘要翻译： 本发明提供制造用于半导体器件的隔离结构的方法。 该方法包括通过图案化的光致抗蚀剂层225和位于衬底205上的等离子体的硬掩模层215在衬底中形成开口，用等离子体修剪光致抗蚀剂层225以形成硬掩模层215的暴露部分215a，去除 具有等离子体的暴露部分215a以形成沟槽引导开口227，并且通过等离子体通过沟槽引导开口227产生沟槽230。

    BONE COMPRESSION PLATE SYSTEM AND METHOD OF USE
    4.
    发明申请
    BONE COMPRESSION PLATE SYSTEM AND METHOD OF USE 有权

    公开(公告)号：US20210128207A1

    公开(公告)日：2021-05-06

    申请号：US16751378

    申请日：2020-01-24

    申请人： Jorge L. Orbay ,  Alexander N. Gil ,  Brian A. Smith

    发明人： Jorge L. Orbay ,  Alexander N. Gil ,  Brian A. Smith

    IPC分类号： A61B17/80

    摘要： Disclosed is a bone compression plate system comprising a substantially elongated first plate having a bone attachment portion and a anchoring portion, the bone attachment portion comprising one or more holes adapted to receive screws for attachment to a bone, the anchoring portion comprising a compression anchor; a substantially elongated second plate having a bone attachment portion and a anchoring portion, the bone attachment portion comprising one or more holes adapted to receive screws for attachment to a bone, the anchoring portion comprising a compression anchor; and a compression screw comprising a male component and a female component, each of the male and female components comprising a head, a shaft, and a tip, the tip of the male component adapted for threaded engagement with the tip of the female component, the head of the male component adapted to engage into, and be retained by the compression anchor in the first plate, and the head of the component adapted to engage into, and be retained by the compression anchor in the second plate.

    Drive current improvement from recessed SiGe incorporation close to gate
    5.
    发明授权
    Drive current improvement from recessed SiGe incorporation close to gate 有权
    驱动目前从嵌入式SiGe并入门口的改进

    公开(公告)号：US07244654B2

    公开(公告)日：2007-07-17

    申请号：US10901568

    申请日：2004-07-29

    申请人： Pr Chidambaram ,  Douglas T. Grider ,  Brian A. Smith ,  Haowen Bu ,  Lindsey Hall

    发明人： Pr Chidambaram ,  Douglas T. Grider ,  Brian A. Smith ,  Haowen Bu ,  Lindsey Hall

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

    摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.

    摘要翻译： 形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。 然后在凹槽中外延生长硅（114），随后在栅极结构的横向边缘上形成侧壁间隔物（118）。 该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。 在凹槽中形成的硅锗位于晶体管沟道附近，用于向通道提供压缩应力，从而有助于改善PMOS型晶体管器件的载流子迁移率。

    Raspberry plant named `Lauren`
    7.
    植物专利
    Raspberry plant named `Lauren` 失效

    公开(公告)号：USPP10610P

    公开(公告)日：1998-09-22

    申请号：US630180

    申请日：1996-04-10

    申请人： Harry Jan Swartz ,  Joseph A. Fiola ,  Herbert D. Stiles ,  Brian A. Smith

    发明人： Harry Jan Swartz ,  Joseph A. Fiola ,  Herbert D. Stiles ,  Brian A. Smith

    摘要： This invention relates to a new and distinct spring bearing red raspberry cultivar named `Lauren` which is capable of producing large fruit of floricanes that ripen 1 to 3 weeks earlier than `Titan`, the only other large fruited cultivar grown in the eastern United States, and several days to weeks earlier than most standard cultivars currently in widespread use. The cultivar is characterized by its moderate suckering ability, its conic, smooth and symmetrical fruit. Additionally, its canes are upright and vigorous, and it does not normally produce a fall crop.

    Pseudomonopulse tracking system with variable coupler and integrated LNA
    9.
    发明申请
    Pseudomonopulse tracking system with variable coupler and integrated LNA 审中-公开
    具有可变耦合器和集成LNA的伪脉冲跟踪系统

    公开(公告)号：US20070279276A1

    公开(公告)日：2007-12-06

    申请号：US11443737

    申请日：2006-05-31

    申请人： James K. Conn ,  James B. Offner ,  Larry P. Serulneck ,  Earl B. Knick ,  Ron Hash ,  Ying-Ming Lee ,  Pete Denney ,  Joseph A. Elam ,  Brian A. Smith

    发明人： James K. Conn ,  James B. Offner ,  Larry P. Serulneck ,  Earl B. Knick ,  Ron Hash ,  Ying-Ming Lee ,  Pete Denney ,  Joseph A. Elam ,  Brian A. Smith

    IPC分类号： G01S13/44 ,  G01S13/66

    CPC分类号： G01S3/325

    摘要： System for dynamically tracking a position of a target with an antenna in a communication system. The system includes an antenna system (410) configured for generating a sum and difference antenna pattern (201-1, 201-2). A sum RF channel (401) is coupled to a sum channel output of the antenna system. A difference RF channel (402) is coupled to a difference channel output of the antenna system. An RF coupler (422-1) is provided that has a first input coupled to the sum RF channel and a second input coupled to the RF difference channel. One or more coupling control devices (418-1, 418-2) selectively vary an effective coupling value as between the difference channel and the sum channel. An antenna tracking error signal is generated at an output of the coupler.

    摘要翻译： 用于在通信系统中用天线动态跟踪目标位置的系统。 该系统包括配置用于产生和差和差分天线方向图（201-1,201-2）的天线系统（410）。 总和RF信道（401）耦合到天线系统的和信道输出。 差分RF信道（402）耦合到天线系统的差分信道输出。 提供RF耦合器（422-1），其具有耦合到和RF通道的第一输入和耦合到RF差分通道的第二输入。 一个或多个耦合控制装置（418-1,418-2）选择性地改变在差信道和和信道之间的有效耦合值。 在耦合器的输出端产生天线跟踪误差信号。

    Method for patterning sub-lithographic features in semiconductor manufacturing
    10.
    发明授权
    Method for patterning sub-lithographic features in semiconductor manufacturing 有权
    在半导体制造中图案化亚光刻特征的方法

    公开(公告)号：US07300883B2

    公开(公告)日：2007-11-27

    申请号：US10930228

    申请日：2004-08-31

    申请人： Francis G. Celii ,  Brian A. Smith ,  James Blatchford ,  Robert Kraft

    发明人： Francis G. Celii ,  Brian A. Smith ,  James Blatchford ,  Robert Kraft

    IPC分类号： H01L21/336 ,  H01L21/302 ,  H01L21/461 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/28123 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

    摘要： A method of forming a gate electrode (24′) for a metal-oxide-semiconductor (MOS) integrated circuit is disclosed. A hardmask layer (26), for example formed of silicon-rich nitride, is deposited over a polysilicon layer (24) from which the gate electrode (24′) is to be formed. An anti-reflective coating, or bottom anti-reflective coating or BARC, layer (29) is then formed over the hardmask layer (26), and photoresist (30) is photolithographically patterned to define the pattern of the gate electrode (24′), although to a wider, photolithographic, width (LW). The pattern is transferred from the photoresist (30) to the BARC layer (29). The remaining elements of the BARC layer (29) are then trimmed, preferably by a timed isotropic etch, to a sub-lithographic width (SW). This pattern is then transferred to the hardmask layer (26) by an anisotropic etch of that layer, using the trimmed BARC elements (29) as a mask. The hardmask layer elements (26′) then mask the etch of the underlying polysilicon layer (24), to define the gate electrodes (24′), having gate widths that are narrower than the minimum dimension available through photolithography.

    摘要翻译： 公开了一种形成用于金属氧化物半导体（MOS）集成电路的栅电极（24'）的方法。 例如由富含硅的氮化物形成的硬掩模层（26）沉积在要形成栅电极（24'）的多晶硅层（24）上。 然后在硬掩模层（26）上形成抗反射涂层或底部抗反射涂层或BARC层（29），光刻图案化光致抗蚀剂（30）以限定栅电极（24'）的图案， ，尽管对于更宽的光刻宽度（LW）。 图案从光致抗蚀剂（30）转移到BARC层（29）。 然后将BARC层（29）的其余元件优选地通过定时各向同性蚀刻修整到亚光刻宽度（SW）。 然后通过该层的各向异性蚀刻，使用修剪的BARC元件（29）作为掩模将该图案转移到硬掩模层（26）。 硬掩模层元件（26'）然后掩蔽下面的多晶硅层（24）的蚀刻，以限定栅电极（24'），栅极宽度比通过光刻可用的最小尺寸窄。