公开(公告)号：US06905943B2

公开(公告)日：2005-06-14

申请号：US10703387

申请日：2003-11-06

申请人： Juanita DeLoach ,  Freidoon Mehrad ,  Brian M. Trentman ,  Troy A. Yocum

发明人： Juanita DeLoach ,  Freidoon Mehrad ,  Brian M. Trentman ,  Troy A. Yocum

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： In one embodiment, a method for forming a semiconductor structure in manufacturing a semiconductor device includes providing a pad layer on a surface of a substrate, providing a nitride layer on the pad layer, and providing a sacrificial oxide layer on the nitride layer. In a first etching step, at least the sacrificial oxide and nitride layers are etched to define opposing substantially vertical surfaces of at least the sacrificial oxide and nitride layers. In a second etching step, the nitride layer is etched such that the opposing substantially vertical surfaces of the nitride layer are recessed from the opposing substantially vertical surfaces of the sacrificial oxide layer, the sacrificial oxide layer substantially preventing the nitride layer from decreasing in thickness as a result of the etching of the nitride layer. In a third etching step, the substrate is etched to form a trench extending into the substrate for purposes of defining one or more isolation regions adjacent the trench.

摘要翻译： 在一个实施例中，在制造半导体器件中形成半导体结构的方法包括在衬底的表面上提供焊盘层，在焊盘层上提供氮化物层，并在氮化物层上提供牺牲氧化物层。 在第一蚀刻步骤中，至少牺牲氧化物层和氮化物层被蚀刻以限定至少牺牲氧化物层和氮化物层的相对的基本垂直的表面。 在第二蚀刻步骤中，蚀刻氮化物层，使得氮化物层的相对的基本上垂直的表面从牺牲氧化物层的相对的基本上垂直的表面凹陷，牺牲氧化物层基本上防止氮化物层的厚度减小 蚀刻氮化物层的结果。 在第三蚀刻步骤中，蚀刻衬底以形成延伸到衬底中的沟槽，用于限定与沟槽相邻的一个或多个隔离区域。

公开(公告)号：US20050101101A1

公开(公告)日：2005-05-12

申请号：US10703387

申请日：2003-11-06

申请人： Juanita DeLoach ,  Freidoon Mehrad ,  Brian Trentman ,  Troy Yocum

发明人： Juanita DeLoach ,  Freidoon Mehrad ,  Brian Trentman ,  Troy Yocum

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： In one embodiment, a method for forming a semiconductor structure in manufacturing a semiconductor device includes providing a pad layer on a surface of a substrate, providing a nitride layer on the pad layer, and providing a sacrificial oxide layer on the nitride layer. In a first etching step, at least the sacrificial oxide and nitride layers are etched to define opposing substantially vertical surfaces of at least the sacrificial oxide and nitride layers. In a second etching step, the nitride layer is etched such that the opposing substantially vertical surfaces of the nitride layer are recessed from the opposing substantially vertical surfaces of the sacrificial oxide layer, the sacrificial oxide layer substantially preventing the nitride layer from decreasing in thickness as a result of the etching of the nitride layer. In a third etching step, the substrate is etched to form a trench extending into the substrate for purposes of defining one or more isolation regions adjacent the trench.

摘要翻译： 在一个实施例中，在制造半导体器件中形成半导体结构的方法包括在衬底的表面上提供焊盘层，在焊盘层上提供氮化物层，并在氮化物层上提供牺牲氧化物层。 在第一蚀刻步骤中，至少牺牲氧化物层和氮化物层被蚀刻以限定至少牺牲氧化物层和氮化物层的相对的基本垂直的表面。 在第二蚀刻步骤中，蚀刻氮化物层，使得氮化物层的相对的基本上垂直的表面从牺牲氧化物层的相对的基本上垂直的表面凹陷，牺牲氧化物层基本上防止氮化物层的厚度减小 蚀刻氮化物层的结果。 在第三蚀刻步骤中，蚀刻衬底以形成延伸到衬底中的沟槽，用于限定与沟槽相邻的一个或多个隔离区域。

公开(公告)号：US07670952B2

公开(公告)日：2010-03-02

申请号：US11690643

申请日：2007-03-23

申请人： Yaw S. Obeng ,  Juanita DeLoach ,  Freidoon Mehrad

发明人： Yaw S. Obeng ,  Juanita DeLoach ,  Freidoon Mehrad

IPC分类号： H01L21/311

CPC分类号： H01L21/823835 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/823871

摘要： A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.

摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底表面上形成金属硅化物栅电极。 该方法还包括将金属硅化物栅电极和衬底表面暴露于清洁过程。 清洁过程包括使用含无水氟化物的进料气体的干等离子体蚀刻和被配置为使金属硅化物栅电极基本上保持不变的热升华。 该方法还包括在衬底表面的源极和漏极区域上沉积金属层并退火衬底表面的金属层和源极和漏极区域以形成金属硅化物源极和漏极接触。

公开(公告)号：US20080230846A1

公开(公告)日：2008-09-25

申请号：US11690643

申请日：2007-03-23

申请人： Yaw S. Obeng ,  Juanita DeLoach ,  Freidoon Mehrad

发明人： Yaw S. Obeng ,  Juanita DeLoach ,  Freidoon Mehrad

IPC分类号： H01L29/76 ,  H01L21/44 ,  H01L29/94 ,  H01L21/461 ,  H01L21/302 ,  H01L31/00

CPC分类号： H01L21/823835 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/823871

摘要： A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.

摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底表面上形成金属硅化物栅电极。 该方法还包括将金属硅化物栅电极和衬底表面暴露于清洁过程。 清洁过程包括使用含无水氟化物的进料气体的干等离子体蚀刻和被配置为使金属硅化物栅电极基本上保持不变的热升华。 该方法还包括在衬底表面的源极和漏极区域上沉积金属层并退火衬底表面的金属层和源极和漏极区域以形成金属硅化物源极和漏极接触。

公开(公告)号：US07422967B2

公开(公告)日：2008-09-09

申请号：US11127669

申请日：2005-05-12

申请人： Juanita DeLoach ,  Lindsey H. Hall ,  Lance S. Robertson ,  Jiong-Ping Lu ,  Donald S. Miles

发明人： Juanita DeLoach ,  Lindsey H. Hall ,  Lance S. Robertson ,  Jiong-Ping Lu ,  Donald S. Miles

IPC分类号： H01L21/3205

CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).

摘要翻译： 本发明提供一种制造半导体器件的方法。 在本发明的一个实施例中，但不限于，用于制造半导体器件的方法包括在衬底（110）上形成栅极结构（120）并且在靠近栅极的衬底（110）中形成源/漏区（190） 结构（120）。 该方法还包括在源极/漏极区（190）中使用含氟等离子体，使用小于约75瓦特的功率电平形成含氟区域（220），在基底（110）上形成金属层（310），以及 含氟区域（220），并且使金属层（310）与含氟区域（220）反应以在源极/漏极区域（190）中形成金属硅化物区域（410）。

公开(公告)号：US20050085047A1

公开(公告)日：2005-04-21

申请号：US10689177

申请日：2003-10-20

申请人： Juanita DeLoach ,  Brian Smith

发明人： Juanita DeLoach ,  Brian Smith

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/823878 ,  H01L21/76232

摘要： The present invention provides a process of manufacturing an isolation structure for use in a semiconductor device. The process includes forming an opening in a substrate through a patterned photoresist layer 225 and a hardmask layer 215 located over the substrate 205 with plasma, trimming the photoresist layer 225 with a plasma to create an exposed portion 215a of the hardmask layer 215, removing the exposed portion 215a with a plasma to create a trench guide opening 227, and creating a trench 230 through the trench guide opening 227 with a plasma.

摘要翻译： 本发明提供制造用于半导体器件的隔离结构的方法。 该方法包括通过图案化的光致抗蚀剂层225和位于衬底205上的等离子体的硬掩模层215在衬底中形成开口，用等离子体修剪光致抗蚀剂层225以形成硬掩模层215的暴露部分215a，去除 具有等离子体的暴露部分215a以形成沟槽引导开口227，并且通过等离子体通过沟槽引导开口227产生沟槽230。

公开(公告)号：US20090079010A1

公开(公告)日：2009-03-26

申请号：US11861421

申请日：2007-09-26

申请人： Juanita DeLoach ,  Jiong-Ping Lu ,  Haowen Bu

发明人： Juanita DeLoach ,  Jiong-Ping Lu ,  Haowen Bu

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/7833

摘要： Semiconductor components are often fabricated that include a nickel silicide layer, e.g., as part of a gate electrode in a transistor component, which may be formed by forming a layer of nickel on a silicon-containing area of the semiconductor substrate, followed by thermally annealing the semiconductor substrate to produce a nickel silicide. However, nickel may tend to diffuse into silicon during the thermal anneal, and may form crystals that undesirably increase the sheet resistance in the transistor. Carbon may be placed with the nickel to serve as a diffusion suppressant and/or to prevent nickel crystal formation during thermal annealing. Methods are disclosed for utilizing this technique, as well as semiconductor components formed in accordance with this technique.

摘要翻译： 通常制造半导体部件，其包括硅化镍层，例如，作为晶体管部件中的栅电极的一部分，其可以通过在半导体衬底的含硅区域上形成镍层，然后进行热退火 半导体衬底以产生硅化镍。 然而，镍可能在热退火期间扩散到硅中，并且可能形成不期望地增加晶体管中的薄层电阻的晶体。 碳可以与镍一起放置以用作扩散抑制剂和/或防止在热退火期间形成镍晶体。 公开了利用该技术的方法以及根据该技术形成的半导体部件。

公开(公告)号：US20090020791A1

公开(公告)日：2009-01-22

申请号：US11778321

申请日：2007-07-16

申请人： Shaofeng Yu ,  Juanita DeLoach ,  Brian A. Smith ,  Yaw S. Obeng ,  Scott Gregory Bushman

发明人： Shaofeng Yu ,  Juanita DeLoach ,  Brian A. Smith ,  Yaw S. Obeng ,  Scott Gregory Bushman

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： Exemplary embodiments provide IC CMOS devices having dual stress layers and methods for their manufacture using a buffer layer stack between the two types of the stress layers. The buffer layer stack can include multiple buffer layers formed between a first type stress layer (e.g., a tensile stress layer) and a second type stress layer (e.g., a compressive stress layer) during the CMOS fabrication. Specifically, the buffer layer stack can be formed after the etching process of the first type stress layer but prior to the etching process of the second type stress layer, and thus to protect the etched first type stress layer during the subsequent etching process of the overlaid second type stress layer. In addition, a portion of the buffer layer stack can be formed between, for example, the compressive stress layer and the underlying PMOS device to enhance their adhesion.

摘要翻译： 示例性实施例提供了具有双应力层的IC CMOS器件及其制造方法，使用两种类型的应力层之间的缓冲层堆叠。 缓冲层堆叠可以包括在CMOS制造期间在第一类型应力层（例如，拉伸应力层）和第二类型应力层（例如，压应力层）之间形成的多个缓冲层。 具体地说，缓冲层堆叠可以在第一类应力层的蚀刻工艺之后但是在第二种应力层的蚀刻工艺之前形成，从而在重叠的随后的蚀刻工艺期间保护蚀刻的第一类型应力层 第二类应力层。 此外，缓冲层堆叠的一部分可以形成在例如压应力层和下面的PMOS器件之间，以增强其粘附性。

公开(公告)号：US08546259B2

公开(公告)日：2013-10-01

申请号：US11861421

申请日：2007-09-26

申请人： Juanita DeLoach ,  Jiong-Ping Lu ,  Haowen Bu

发明人： Juanita DeLoach ,  Jiong-Ping Lu ,  Haowen Bu

IPC分类号： H01L21/44

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/7833

摘要： Semiconductor components are often fabricated that include a nickel silicide layer, e.g., as part of a gate electrode in a transistor component, which may be formed by forming a layer of nickel on a silicon-containing area of the semiconductor substrate, followed by thermally annealing the semiconductor substrate to produce a nickel silicide. However, nickel may tend to diffuse into silicon during the thermal anneal, and may form crystals that undesirably increase the sheet resistance in the transistor. Carbon may be placed with the nickel to serve as a diffusion suppressant and/or to prevent nickel crystal formation during thermal annealing. Methods are disclosed for utilizing this technique, as well as semiconductor components formed in accordance with this technique.

摘要翻译： 通常制造半导体部件，其包括硅化镍层，例如，作为晶体管部件中的栅电极的一部分，其可以通过在半导体衬底的含硅区域上形成镍层，然后进行热退火 半导体衬底以产生硅化镍。 然而，镍可能在热退火期间扩散到硅中，并且可能形成不期望地增加晶体管中的薄层电阻的晶体。 碳可以与镍一起放置以用作扩散抑制剂和/或防止在热退火期间形成镍晶体。 公开了利用该技术的方法以及根据该技术形成的半导体部件。

公开(公告)号：US07320927B2

公开(公告)日：2008-01-22

申请号：US10689177

申请日：2003-10-20

申请人： Juanita DeLoach ,  Brian A. Smith

发明人： Juanita DeLoach ,  Brian A. Smith

IPC分类号： H01L21/762

CPC分类号： H01L21/823878 ,  H01L21/76232

摘要： The present invention provides a process of manufacturing an isolation structure for use in a semiconductor device. The process includes forming an opening in a substrate through a patterned photoresist layer 225 and a hardmask layer 215 located over the substrate 205 with plasma, trimming the photoresist layer 225 with a plasma to create an exposed portion 215a of the hardmask layer 215, removing the exposed portion 215a with a plasma to create a trench guide opening 227, and creating a trench 230 through the trench guide opening 227 with a plasma.

摘要翻译： 本发明提供制造用于半导体器件的隔离结构的方法。 该方法包括通过图案化的光致抗蚀剂层225和位于衬底205上的等离子体的硬掩模层215在衬底中形成开口，用等离子体修剪光致抗蚀剂层225以形成硬掩模层215的暴露部分215a，去除 具有等离子体的暴露部分215a以形成沟槽引导开口227，并且通过等离子体通过沟槽引导开口227产生沟槽230。