公开(公告)号：US06905943B2

公开(公告)日：2005-06-14

申请号：US10703387

申请日：2003-11-06

申请人： Juanita DeLoach ,  Freidoon Mehrad ,  Brian M. Trentman ,  Troy A. Yocum

发明人： Juanita DeLoach ,  Freidoon Mehrad ,  Brian M. Trentman ,  Troy A. Yocum

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： In one embodiment, a method for forming a semiconductor structure in manufacturing a semiconductor device includes providing a pad layer on a surface of a substrate, providing a nitride layer on the pad layer, and providing a sacrificial oxide layer on the nitride layer. In a first etching step, at least the sacrificial oxide and nitride layers are etched to define opposing substantially vertical surfaces of at least the sacrificial oxide and nitride layers. In a second etching step, the nitride layer is etched such that the opposing substantially vertical surfaces of the nitride layer are recessed from the opposing substantially vertical surfaces of the sacrificial oxide layer, the sacrificial oxide layer substantially preventing the nitride layer from decreasing in thickness as a result of the etching of the nitride layer. In a third etching step, the substrate is etched to form a trench extending into the substrate for purposes of defining one or more isolation regions adjacent the trench.

摘要翻译： 在一个实施例中，在制造半导体器件中形成半导体结构的方法包括在衬底的表面上提供焊盘层，在焊盘层上提供氮化物层，并在氮化物层上提供牺牲氧化物层。 在第一蚀刻步骤中，至少牺牲氧化物层和氮化物层被蚀刻以限定至少牺牲氧化物层和氮化物层的相对的基本垂直的表面。 在第二蚀刻步骤中，蚀刻氮化物层，使得氮化物层的相对的基本上垂直的表面从牺牲氧化物层的相对的基本上垂直的表面凹陷，牺牲氧化物层基本上防止氮化物层的厚度减小 蚀刻氮化物层的结果。 在第三蚀刻步骤中，蚀刻衬底以形成延伸到衬底中的沟槽，用于限定与沟槽相邻的一个或多个隔离区域。

公开(公告)号：US20050101101A1

公开(公告)日：2005-05-12

申请号：US10703387

申请日：2003-11-06

申请人： Juanita DeLoach ,  Freidoon Mehrad ,  Brian Trentman ,  Troy Yocum

发明人： Juanita DeLoach ,  Freidoon Mehrad ,  Brian Trentman ,  Troy Yocum

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： In one embodiment, a method for forming a semiconductor structure in manufacturing a semiconductor device includes providing a pad layer on a surface of a substrate, providing a nitride layer on the pad layer, and providing a sacrificial oxide layer on the nitride layer. In a first etching step, at least the sacrificial oxide and nitride layers are etched to define opposing substantially vertical surfaces of at least the sacrificial oxide and nitride layers. In a second etching step, the nitride layer is etched such that the opposing substantially vertical surfaces of the nitride layer are recessed from the opposing substantially vertical surfaces of the sacrificial oxide layer, the sacrificial oxide layer substantially preventing the nitride layer from decreasing in thickness as a result of the etching of the nitride layer. In a third etching step, the substrate is etched to form a trench extending into the substrate for purposes of defining one or more isolation regions adjacent the trench.

摘要翻译： 在一个实施例中，在制造半导体器件中形成半导体结构的方法包括在衬底的表面上提供焊盘层，在焊盘层上提供氮化物层，并在氮化物层上提供牺牲氧化物层。 在第一蚀刻步骤中，至少牺牲氧化物层和氮化物层被蚀刻以限定至少牺牲氧化物层和氮化物层的相对的基本垂直的表面。 在第二蚀刻步骤中，蚀刻氮化物层，使得氮化物层的相对的基本上垂直的表面从牺牲氧化物层的相对的基本上垂直的表面凹陷，牺牲氧化物层基本上防止氮化物层的厚度减小 蚀刻氮化物层的结果。 在第三蚀刻步骤中，蚀刻衬底以形成延伸到衬底中的沟槽，用于限定与沟槽相邻的一个或多个隔离区域。

公开(公告)号：US07670952B2

公开(公告)日：2010-03-02

申请号：US11690643

申请日：2007-03-23

申请人： Yaw S. Obeng ,  Juanita DeLoach ,  Freidoon Mehrad

发明人： Yaw S. Obeng ,  Juanita DeLoach ,  Freidoon Mehrad

IPC分类号： H01L21/311

CPC分类号： H01L21/823835 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/823871

摘要： A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.

摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底表面上形成金属硅化物栅电极。 该方法还包括将金属硅化物栅电极和衬底表面暴露于清洁过程。 清洁过程包括使用含无水氟化物的进料气体的干等离子体蚀刻和被配置为使金属硅化物栅电极基本上保持不变的热升华。 该方法还包括在衬底表面的源极和漏极区域上沉积金属层并退火衬底表面的金属层和源极和漏极区域以形成金属硅化物源极和漏极接触。

公开(公告)号：US06818526B2

公开(公告)日：2004-11-16

申请号：US10263511

申请日：2002-10-02

申请人： Freidoon Mehrad ,  Zhihao Chen ,  Juanita Deloach

发明人： Freidoon Mehrad ,  Zhihao Chen ,  Juanita Deloach

IPC分类号： H01L21336

CPC分类号： H01L21/76224

摘要： A method of fabricating a shallow trench isolation structure includes forming outwardly of a semiconductor layer a first oxide layer. A nitride layer is formed outwardly of the first oxide layer. A second oxide layer is formed outwardly of the nitride layer. A trench is formed through the first oxide layer, the nitride layer, and the second oxide layer and into the semiconductor layer. With the second oxide layer protecting an upper surface of the nitride layer, the nitride layer is etched to form a lateral recessed side boundary of the trench at the nitride layer. The shallow trench isolation layer is formed in the trench.

摘要翻译： 制造浅沟槽隔离结构的方法包括在半导体层向外形成第一氧化物层。 在第一氧化物层的外部形成氮化物层。 在氮化物层的外侧形成第二氧化物层。 通过第一氧化物层，氮化物层和第二氧化物层形成沟槽并进入半导体层。 利用第二氧化物层保护氮化物层的上表面，蚀刻氮化物层以在氮化物层处形成沟槽的侧凹侧边界。 在沟槽中形成浅沟槽隔离层。

公开(公告)号：US20080230846A1

公开(公告)日：2008-09-25

申请号：US11690643

申请日：2007-03-23

申请人： Yaw S. Obeng ,  Juanita DeLoach ,  Freidoon Mehrad

发明人： Yaw S. Obeng ,  Juanita DeLoach ,  Freidoon Mehrad

IPC分类号： H01L29/76 ,  H01L21/44 ,  H01L29/94 ,  H01L21/461 ,  H01L21/302 ,  H01L31/00

CPC分类号： H01L21/823835 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/823871

摘要： A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.

摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底表面上形成金属硅化物栅电极。 该方法还包括将金属硅化物栅电极和衬底表面暴露于清洁过程。 清洁过程包括使用含无水氟化物的进料气体的干等离子体蚀刻和被配置为使金属硅化物栅电极基本上保持不变的热升华。 该方法还包括在衬底表面的源极和漏极区域上沉积金属层并退火衬底表面的金属层和源极和漏极区域以形成金属硅化物源极和漏极接触。

公开(公告)号：US20110031557A1

公开(公告)日：2011-02-10

申请号：US12908140

申请日：2010-10-20

申请人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

发明人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

摘要： A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.

摘要翻译： 一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。 栅极电介质层形成在PMOS区域和NMOS区域上。 在栅极电介质层上形成原始栅电极层。 栅极掩模层被施加在栅极电极层上。 蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。 为PMOS器件和NMOS器件形成源极和漏极区域。 为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。 在沟槽中形成包括置换栅极的金属，并且完成IC的制造。

公开(公告)号：US07601575B2

公开(公告)日：2009-10-13

申请号：US11072779

申请日：2005-03-04

申请人： Haowen Bu ,  Shashank Ekbote ,  Rajesh Khamankar ,  Shaoping Tang ,  Freidoon Mehrad

发明人： Haowen Bu ,  Shashank Ekbote ,  Rajesh Khamankar ,  Shaoping Tang ,  Freidoon Mehrad

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/44

CPC分类号： H01L29/0847 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845 ,  Y10S438/902

摘要： The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.

摘要翻译： 本发明通过提供一种提高沟道电子迁移率而不会使PMOS晶体管器件基本上衰减的帽退火工艺来促进半导体器件的操作和制造。 该方法使用氧化物/氮化物复合帽来改变通道区域上的活性掺杂剂分布。 在退火过程中，掺杂剂在沟道区中迁移出Si / SiO 2，从而改变沟道区的掺杂物分布。 这种改变的形状通常改善了沟道迁移率，从而提高了晶体管的性能并允许更小的密度设计。

公开(公告)号：US20090050976A1

公开(公告)日：2009-02-26

申请号：US11844832

申请日：2007-08-24

申请人： Freidoon Mehrad ,  Frank S. Johnson

发明人： Freidoon Mehrad ,  Frank S. Johnson

IPC分类号： H01L21/3205 ,  H01L29/78

CPC分类号： H01L21/823835

摘要： An improved method of forming a fully silicided (FUSI) gate in both NMOS and PMOS transistors of the same MOS device is disclosed. In one example, the method comprises forming a first silicide in at least a top portion of a gate electrode of the PMOS devices and not over the NMOS devices. The method further comprises concurrently forming a second silicide in at least a top portion of a gate electrode of both the NMOS and PMOS devices, and forming a FUSI gate silicide of the gate electrodes. In one embodiment, the thickness of the second silicide is greater than the first silicide by an amount which compensates for a difference in the rates of silicide formation between the NMOS and PMOS devices.

摘要翻译： 公开了在相同MOS器件的NMOS和PMOS晶体管中形成完全硅化（FUSI）栅极的改进方法。 在一个示例中，该方法包括在PMOS器件的栅电极的至少顶部部分中形成第一硅化物，而不是在NMOS器件上形成。 该方法还包括在NMOS和PMOS器件的栅电极的至少顶部中同时形成第二硅化物，以及形成栅电极的FUSI栅极硅化物。 在一个实施例中，第二硅化物的厚度大于第一硅化物的量，该量补偿了NMOS和PMOS器件之间的硅化物形成速率的差异。

公开(公告)号：US07448395B2

公开(公告)日：2008-11-11

申请号：US10894374

申请日：2004-07-19

申请人： Jiong-Ping Lu ,  Freidoon Mehrad ,  Lindsey Hall ,  Vivian Liu ,  Clint Montgomery ,  Scott Johnson

发明人： Jiong-Ping Lu ,  Freidoon Mehrad ,  Lindsey Hall ,  Vivian Liu ,  Clint Montgomery ,  Scott Johnson

IPC分类号： B08B6/00 ,  C25F1/00 ,  C25F3/30 ,  C25F5/00

CPC分类号： H01L21/28518 ,  H01L21/02046 ,  H01L21/0206 ,  H01L21/28052 ,  H01L29/665

摘要： The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.

摘要翻译： 本发明在将钴层124沉积在硅衬底和/或多晶硅材料上之前基本上从干等离子体蚀刻工艺110去除干蚀刻残留物。 随后，进行一个或多个退火工艺128，其使钴与硅反应，从而形成硅化钴区域。 残留在沉积的钴和下面的硅之间的干蚀刻残留物的缺乏允许用期望的硅化物片和接触电阻基本上均匀地形成硅化钴区域。 通过执行第一清洁操作112，然后进行包括合适的清洁溶液的延长清洁操作114，基本上去除了干蚀刻残留物。 第一次清洁操作通常去除一些但不是全部的干蚀刻残留物。 延长的清洁操作114在更高的温度和/或延长的持续时间内进行，并且基本上去除了在第一清洁操作112之后残留的干蚀刻残留物。

公开(公告)号：US20080265344A1

公开(公告)日：2008-10-30

申请号：US11741519

申请日：2007-04-27

申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.

摘要翻译： 同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。 示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层 所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及 活跃区域。