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公开(公告)号：US4860288A
公开(公告)日：1989-08-22
申请号：US112916
申请日：1987-10-23
IPC分类号： G01R31/28 , G01R31/3185 , G06F1/04 , H01L21/66 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G01R31/318552
摘要： This application teaches that more accurate measurements of clock skew can be had by providing a clock monitor pin directly connected to the clock bus internal to the VLSI chip.
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2.发明授权Flexible VLSI on-chip maintenance and test system with unit I/O cell design 失效灵活的VLSI片上维护和测试系统，具有单元I / O单元设计
公开(公告)号：US4912709A
公开(公告)日：1990-03-27
申请号：US112920
申请日：1987-10-23
申请人： Judy L. Teske , Daniel J. Baxter , Don A. Daane , Brian D. Borchers , David H. Allen , Michael F. Maas
发明人： Judy L. Teske , Daniel J. Baxter , Don A. Daane , Brian D. Borchers , David H. Allen , Michael F. Maas
IPC分类号： G01R31/28 , G01R31/3185 , G06F1/04 , H01L21/66 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G01R31/318538
摘要： This application describes a peripheral cell structure for VLSI chips that requires the use of standard cells having both input and output capability connected to nearly all of the signal carrying pins. The cells function is alterable (to input or output and to where the data input signals originate) by control signals which may originate with a control register. The clock input signal is split into two independent signals to selectively disable the input or output registers, thus allowing the control register to be changed without affecting the contents of the other two registers. An early signal is also provided to prepare for mode changes.
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公开(公告)号：US06734743B2
公开(公告)日：2004-05-11
申请号：US10236329
申请日：2002-09-06
IPC分类号： H03B520
CPC分类号： G11C29/50012 , G01R31/31922 , G01R31/31937 , G11C29/50 , G11C29/56 , G11C29/56012
摘要： An embodiment of the invention is circuitry 25 that contains a programmable delay 8 and a pulse generator 16 that send clock signals of a certain frequency to a device under test 1. The programmable delay 8 increases the frequency of the clock signal to the device under test 1 until the device under test fails. The cycle time measurement of the device under test 1 is the period of maximum frequency at which the device under test 1 operates properly.
摘要翻译： 本发明的实施例是包含可编程延迟8的电路25和向特定频率的时钟信号发送到被测器件1的脉冲发生器16.可编程延迟8将时钟信号的频率增加到被测器件 1，直到被测设备失败。 被测设备1的周期时间测量是被测设备1正常工作的最大频率周期。
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公开(公告)号：US07210078B2
公开(公告)日：2007-04-24
申请号：US10230543
申请日：2002-08-29
CPC分类号： G11C29/003
摘要： A method for evaluating an output of a sequential circuit 2 by storing a series of output pulses from the sequential circuit 2 and determining whether the output pulses 4 toggled as desired. Also a circuit 1 for evaluating an output 4 of a sequential circuit 2 that determines if the output pulses 4 toggled as desired.
摘要翻译： 一种用于通过存储来自顺序电路2的一系列输出脉冲并确定输出脉冲4是否按需要切换来评估时序电路2的输出的方法。 还有一个用于评估顺序电路2的输出4的电路1，其确定输出脉冲4是否根据需要切换。
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公开(公告)号：US06909301B2
公开(公告)日：2005-06-21
申请号：US10236328
申请日：2002-09-06
CPC分类号： G11C29/50012 , G01R31/3016 , G11C29/14 , G11C29/50
摘要： An embodiment of the invention is a method for measuring access time where the frequency of a ring oscillator is measured with and without a device under test 1 in the ring. Those two frequencies are compared to calculate the access time of the device under test 1. Another embodiment of the invention is circuitry 25 that measures the frequency of a ring oscillator with and without a device under test 1. Again the two frequencies are compared to calculate the access time of the device under test 1.
摘要翻译： 本发明的一个实施例是一种测量接入时间的方法，其中测量环路振荡器的频率是否具有环中的被测器件1。 比较这两个频率来计算被测设备1的访问时间。 本发明的另一实施例是测量具有和不具有被测器件1的环形振荡器的频率的电路25。 将两个频率再次进行比较，以计算被测器件1的访问时间。
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公开(公告)号：US06799134B2
公开(公告)日：2004-09-28
申请号：US10216455
申请日：2002-08-09
IPC分类号： G06F1900
CPC分类号： G11C29/12015 , G01R31/3016 , G01R31/31725 , G01R31/318522 , G11C29/02 , G11C29/50012
摘要： A method and circuit for verifying the burst-mode operation and the frequency characterization of a self-timed sequential circuit 2 in burst mode by detecting and measuring an output 15 of the self-timed sequential circuit 2.
摘要翻译： 一种用于通过检测和测量自定时序列电路2的输出15来验证突发模式中的自定时顺序电路2的突发模式操作和频率表征的方法和电路。
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