公开(公告)号：US08599622B2

公开(公告)日：2013-12-03

申请号：US13176950

申请日：2011-07-06

申请人： Juhyung Kim ,  Changseok Kang ,  Hansoo Kim ,  Byeong-In Choe

发明人： Juhyung Kim ,  Changseok Kang ,  Hansoo Kim ,  Byeong-In Choe

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/32

摘要： An erase method of a charge trap flash memory device, the method including receiving a temperature detection result, and performing an erase operation based on the temperature detection result, wherein the erase operation includes an erase execution interval, an erase verify interval and a delay time between the erase execution interval and the erase verify interval, wherein the erase operation changes a level of a word line voltage applied to word lines during the erase execution interval, a length of the delay time, or a level of the word line voltage applied to the word lines during the delay time.

摘要翻译： 一种电荷捕捉闪存器件的擦除方法，该方法包括接收温度检测结果，并且基于温度检测结果执行擦除操作，其中擦除操作包括擦除执行间隔，擦除验证间隔和延迟时间 在所述擦除执行间隔和所述擦除验证间隔之间，其中所述擦除操作改变在所述擦除执行间隔期间施加到字线的字线电压的电平，所述延迟时间的长度，或施加到所述擦除执行间隔的字线电压的电平 延迟时间内的字线。

公开(公告)号：US20140048868A1

公开(公告)日：2014-02-20

申请号：US13966866

申请日：2013-08-14

申请人： Juhyung Kim ,  Yoocheol Shin

发明人： Juhyung Kim ,  Yoocheol Shin

IPC分类号： H01L29/792

CPC分类号： H01L29/7926 ,  H01L27/11582 ,  H01L29/66833

摘要： A three-dimensional (3D) semiconductor memory device may include an electrode structure extending in a first direction and including insulating patterns and horizontal electrodes stacked on a substrate, a semiconductor pillar penetrating the electrode structure and connected to the substrate, a charge storage layer between the semiconductor pillar and the electrode structure, a tunnel insulating layer between the charge storage layer and the semiconductor pillar, and a blocking insulating layer between the charge storage layer and the electrode structure. A first horizontal electrode of the horizontal electrodes includes a gate electrode and a metal stopper between the gate electrode and the blocking insulating layer.

摘要翻译： 三维（3D）半导体存储器件可以包括在第一方向上延伸的电极结构，其包括堆叠在衬底上的绝缘图案和水平电极，穿透电极结构并连接到衬底的半导体柱，电荷存储层， 半导体柱和电极结构，电荷存储层和半导体柱之间的隧道绝缘层，以及电荷存储层和电极结构之间的阻挡绝缘层。 水平电极的第一水平电极包括在栅电极和阻挡绝缘层之间的栅电极和金属阻挡层。

公开(公告)号：US20140035026A1

公开(公告)日：2014-02-06

申请号：US13800872

申请日：2013-03-13

申请人： Byong-hyun Jang ,  Juhyung Kim ,  Woonkyung Lee ,  Jaegoo Lee ,  Chaeho Kim ,  Junkyu Yang ,  Phil Ouk Nam ,  Jaeyoung Ahn ,  Kihyun Hwang

发明人： Byong-hyun Jang ,  Juhyung Kim ,  Woonkyung Lee ,  Jaegoo Lee ,  Chaeho Kim ,  Junkyu Yang ,  Phil Ouk Nam ,  Jaeyoung Ahn ,  Kihyun Hwang

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L29/792 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

摘要翻译： 一种半导体存储器件及其制造方法。 该器件包括垂直堆叠在衬底的顶表面上的多个栅极，该衬底的顶表面上形成有在该衬底中形成的外延层，垂直穿过该栅极的垂直沟道以与该外延层电连接;以及存储层，设置在该垂直沟道 和大门。 外延层具有位于最下面一个栅极的底表面和基板的顶表面之间的高度的顶表面。