利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

16 条记录 (耗时 0.045 秒)

    NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME
    2.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME 审中-公开
    非易失性存储器件及其形成方法

    公开(公告)号：US20110049610A1

    公开(公告)日：2011-03-03

    申请号：US12845375

    申请日：2010-07-28

    申请人： Junkyu Yang ,  Jaeyoung Ahn ,  Young-Geun Park ,  Kihyun Hwang ,  Dongwoon Shin ,  Juyul Lee

    发明人： Junkyu Yang ,  Jaeyoung Ahn ,  Young-Geun Park ,  Kihyun Hwang ,  Dongwoon Shin ,  Juyul Lee

    IPC分类号： H01L29/792

    CPC分类号： H01L29/513 ,  G11C16/0466 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/792

    摘要： Provided are a nonvolatile memory device and a method of forming the same. The nonvolatile memory device includes: a semiconductor substrate including a device isolation layer defining an active region; a tunnel insulating layer on the active region; a charge trapping layer on the tunnel insulating layer; a blocking insulating layer on the charge trapping layer and the device isolation layer; a gate electrode on the blocking insulating layer; and a barrier capping layer formed between the device isolation layer and the blocking insulating layer.

    摘要翻译： 提供一种非易失性存储器件及其形成方法。 非易失性存储器件包括：半导体衬底，其包括限定有源区的器件隔离层; 有源区上的隧道绝缘层; 隧道绝缘层上的电荷捕获层; 电荷俘获层和器件隔离层上的阻挡绝缘层; 阻挡绝缘层上的栅电极; 以及在器件隔离层和阻挡绝缘层之间形成的阻挡层覆盖层。

    Nonvolatile Memory Devices And Methods Of Manufacturing The Same
    3.
    发明申请
    Nonvolatile Memory Devices And Methods Of Manufacturing The Same 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20120104485A1

    公开(公告)日：2012-05-03

    申请号：US13281784

    申请日：2011-10-26

    申请人： Junkyu Yang ,  HongSuk Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  Guk-Hyon Yon

    发明人： Junkyu Yang ,  HongSuk Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  Guk-Hyon Yon

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11521 ,  H01L21/764 ,  H01L27/11568

    摘要： A method of manufacturing a nonvolatile memory device includes forming a tunnel dielectric layer, a charge storage layer, and a hard mask layer on a substrate in sequential order. Active portions are defined by forming trenches in the substrate. A tunnel dielectric pattern, a preliminary charge storage pattern, and a hard mask pattern are formed on each of the active portions in sequential order by sequentially patterning the hard mask layer, the charge storage layer, the tunnel dielectric layer, and the substrate. A capping pattern is formed covering an upper surface of the trenches such that a first void remains in a lower portion of the trenches, the capping pattern including etch particles formed by etching the hard mask pattern through a sputtering etch process.

    摘要翻译： 一种制造非易失性存储器件的方法包括在衬底上依次形成隧道介电层，电荷存储层和硬掩模层。 通过在衬底中形成沟槽来限定活性部分。 通过对硬掩模层，电荷存储层，隧道介电层和衬底进行顺序构图，按顺序在有源部分的每一个上形成隧道电介质图案，初电电荷存储图案和硬掩模图案。 形成覆盖沟槽的上表面的覆盖图案，使得第一空隙保留在沟槽的下部，封盖图案包括通过溅射蚀刻工艺蚀刻硬掩模图案形成的蚀刻颗粒。

    Three-dimensional semiconductor memory devices
    8.
    发明授权
    Three-dimensional semiconductor memory devices 有权
    三维半导体存储器件

    公开(公告)号：US08598647B2

    公开(公告)日：2013-12-03

    申请号：US13291519

    申请日：2011-11-08

    申请人： Dongwoo Kim ,  Toshiro Nakanishi ,  SeungHyun Lim ,  Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn

    发明人： Dongwoo Kim ,  Toshiro Nakanishi ,  SeungHyun Lim ,  Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

    摘要： Provided are three-dimensional semiconductor devices. The device includes conductive patterns stacked on a substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern includes a first doped region disposed adjacent to at least one of the conductive patterns, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

    摘要翻译： 提供三维半导体器件。 该器件包括堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案包括邻近至少一个导电图案设置的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

    Semiconductor device and method of fabricating the same
    10.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09536897B2

    公开(公告)日：2017-01-03

    申请号：US14695249

    申请日：2015-04-24

    申请人： Dongchul Yoo ,  Chaeho Kim ,  Jaeyoung Ahn ,  Woong Lee

    发明人： Dongchul Yoo ,  Chaeho Kim ,  Jaeyoung Ahn ,  Woong Lee

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    摘要： A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole.

    摘要翻译： 三维半导体器件可以包括包括单元阵列区域，字线接触区域和外围电路区域的基板，堆叠在基板上以从单元阵列区域延伸到字线接触区域的栅电极，通道 穿透单元阵列区域上的栅电极并暴露基板的有源区域，穿过字线接触区域上的栅电极的裸孔，并暴露设置在基板上的器件隔离层，以及设置在基极上的半导体图案 通道孔，但不在虚拟孔中。