公开(公告)号：US4873672A

公开(公告)日：1989-10-10

申请号：US51715

申请日：1987-05-20

申请人： Jun Etoh ,  Katsuhiro Shimohigashi ,  Kazuyuki Miyazawa ,  Katsutaka Kimura ,  Takesada Akiba

发明人： Jun Etoh ,  Katsuhiro Shimohigashi ,  Kazuyuki Miyazawa ,  Katsutaka Kimura ,  Takesada Akiba

IPC分类号： G11C11/401 ,  G11C11/4072 ,  G11C11/4078 ,  G11C11/409

CPC分类号： G11C11/4078 ,  G11C11/4072

摘要： This invention relates to a semiconductor memory having a high speed operation and a high integration density. When a high integration semiconductor memory is applied to a large scale computer system, storage data must be erased at a high speed for data security. The present invention erases the storage data by a method which is different from the write method of conventional prior art. In the invention, the erasing operation is made by continuously selecting word lines while sense amplifiers are kept in this on-state. The present invention includes a control circuit for attaining such an operation, and can be used for a semiconductor memory implemented in a computer system accessed by a plurality of users.

摘要翻译： 本发明涉及具有高速运算和高集成密度的半导体存储器。 当将高集成半导体存储器应用于大规模计算机系统时，为了数据安全，必须高速擦除存储数据。 本发明通过与传统现有技术的写入方法不同的方法擦除存储数据。 在本发明中，通过在感测放大器保持在该接通状态的同时连续选择字线来进行擦除操作。 本发明包括用于实现这种操作的控制电路，并且可以用于由多个用户访问的计算机系统中实现的半导体存储器。

公开(公告)号：US5467314A

公开(公告)日：1995-11-14

申请号：US277430

申请日：1994-07-18

申请人： Kazuyuki Miyazawa ,  Katsuhiro Shimohigashi ,  Jun Etoh ,  Katsutaka Kimura

发明人： Kazuyuki Miyazawa ,  Katsuhiro Shimohigashi ,  Jun Etoh ,  Katsutaka Kimura

IPC分类号： G11C11/401 ,  G01R31/317 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C7/00

CPC分类号： G11C29/46 ,  G01R31/31701

摘要： In an address multiplexed dynamic random access memory (RAM) which has both a normal operation mode and a test mode capability, the test mode is initiated in response to particular signal level combinations of both the row address strobe (RAS) and column address strobe (CAS) signals and the write enable (WE) signal. Since the signal level combinations employed in connection with implementing the test mode are unused in the normal operating mode of the dynamic RAM, additional external terminals are unneeded. This dynamic RAM employs multiplexing circuitry on both the input side as well as on the output side of the dynamic RAM, which multiplexing circuitry is controlled during normal operation by select signals from a decoder and during the test mode by a test signal which allows accessing of data at all of the common complementary data lines by the testing circuitry so as to determine whether there is consistency or inconsistency of the data being read out for testing.

摘要翻译： 在具有正常操作模式和测试模式能力的地址多路复用动态随机存取存储器（RAM）中，测试模式是响应于行地址选通（＆amp; Upbar＆R）和列地址选通 （＆upbar＆C）信号和写使能（＆upbar＆W）信号。 由于在动态RAM的正常操作模式中不使用与实现测试模式相关的信号电平组合，因此不需要额外的外部终端。 该动态RAM在动态RAM的输入侧和输出侧都采用多路复用电路，该复用电路在正常操作期间通过来自解码器的选择信号以及在测试模式期间通过允许访问的测试信号 通过测试电路在所有公共补充数据线上的数据，以便确定正在读出的用于测试的数据是否一致或不一致。

公开(公告)号：US5117393A

公开(公告)日：1992-05-26

申请号：US648885

申请日：1991-01-31

申请人： Kazuyuki Miyazawa ,  Katsuhiro Shimohigashi ,  Jun Etoh ,  Katsutaka Kimura

发明人： Kazuyuki Miyazawa ,  Katsuhiro Shimohigashi ,  Jun Etoh ,  Katsutaka Kimura

IPC分类号： G11C11/401 ,  G01R31/317 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46

CPC分类号： G11C29/46 ,  G01R31/31701

摘要： An address multiplexed dynamic RAM device is provided which is capable of initiating (setting) and terminating (resetting) the test mode in response to the signal level combinations of the row address and column address strobe signals and the write enable signal. The signal level combinations employed correspond to those which are unused in the normal operating mode thereby obviating the need for providing additional external control signal terminals. In addition to writing predetermined data in selected memory cells during the test mode, verficiation of the predetermined data is also implemented during the read phase of the test mode.

公开(公告)号：US5331596A

公开(公告)日：1994-07-19

申请号：US887802

申请日：1992-05-26

申请人： Kazuyuki Miyazawa ,  Katsuhiro Shimohigashi ,  Jun Etoh ,  Katsutaka Kimura

发明人： Kazuyuki Miyazawa ,  Katsuhiro Shimohigashi ,  Jun Etoh ,  Katsutaka Kimura

IPC分类号： G11C11/401 ,  G01R31/317 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C11/407

CPC分类号： G11C29/46 ,  G01R31/31701

摘要： An address multiplexed dynamic random access memory (RAM) which has both a normal operation mode and a test mode capability is provided. The test mode is initiated in response to particular signal level combinations of both the row address strobe (RAS) and column address strobe (CAS) signals and the write enable (WE) signal. Since the signal level combinations employed in connection with implementing the test mode are unused in the normal operating mode of the dynamic RAM, additional external terminals are unneeded. This dynamic RAM employs multiplexing circuitry on both the input side as well as on the output side of the dynamic RAM, which multiplexing circuitry is controlled during normal operation by select signals from a decoder and during the test mode by a test signal which allows accessing of data at all of the common complementary data lines by the testing circuitry so as to determine whether there is consistency or inconsistency of the data being read out for testing.

摘要翻译： 提供具有正常操作模式和测试模式能力的地址多路复用动态随机存取存储器（RAM）。 响应于行地址选通（＆upbar＆R）和列地址选通（＆upbar＆C）信号和写使能（＆upbar＆W）信号的特定信号电平组合，启动测试模式。 由于在动态RAM的正常操作模式中不使用与实现测试模式相关的信号电平组合，因此不需要额外的外部终端。 该动态RAM在动态RAM的输入侧和输出侧都采用多路复用电路，该复用电路在正常操作期间通过来自解码器的选择信号以及在测试模式期间通过允许访问的测试信号 通过测试电路在所有公共补充数据线上的数据，以便确定正在读出的用于测试的数据是否一致或不一致。

公开(公告)号：US4811299A

公开(公告)日：1989-03-07

申请号：US41070

申请日：1987-04-22

申请人： Kazuyuki Miyazawa ,  Katsuhiro Shimohigashi ,  Jun Etoh ,  Katsutaka Kimura

发明人： Kazuyuki Miyazawa ,  Katsuhiro Shimohigashi ,  Jun Etoh ,  Katsutaka Kimura

IPC分类号： G11C11/401 ,  G01R31/317 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C29/46 ,  G01R31/31701

摘要： Disclosed is a dynamic RAM device capable of initiating and cancelling the test mode in response to the combinations of the row address and column address strobe signals with the write enable signal, which combinations are left unused in the normal operating mode, instead of increasing the number of external control signals.

摘要翻译： 公开了一种动态RAM装置，其能够响应于行地址和列地址选通信号与写使能信​​号的组合而启动和取消测试模式，这些组合在正常操作模式下不被使用，而不是增加数量 的外部控制信号。

公开(公告)号：US4992985A

公开(公告)日：1991-02-12

申请号：US319693

申请日：1989-03-07

申请人： Kazuyuki Miyazawa ,  Katsuhiro Shimohigashi ,  Jun Etoh ,  Katsutaka Kimura

发明人： Kazuyuki Miyazawa ,  Katsuhiro Shimohigashi ,  Jun Etoh ,  Katsutaka Kimura

IPC分类号： G11C11/401 ,  G01R31/317 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46

CPC分类号： G11C29/46 ,  G01R31/31701

摘要： An address multiplexed dynamic RAM device is provided which is capable of initiating (setting) and terminating (resetting) the test mode in response to the signal level combinations of the row address and column address strobe signals with the write enable signal, which signal level combinations correspond to those which are otherwise left unused in the normal operating mode thereby obviating the requirement of an additional external control signal terminal. Such initiating of the test mode can be effected by setting the RAS signal of the DRAM at a logic "low" level when the CAS signal and the WE signal are at a logic "low" level. Clearing or resetting thereof is effected by the same combination sequence, except that the WE signal is at a logic "high" level. The setting or initiating of a test mode is also implemented by the additional combination of one of the row address signal bits, e.g. the most significant bit.

公开(公告)号：US5151772A

公开(公告)日：1992-09-29

申请号：US616705

申请日：1990-11-20

申请人： Yasushi Takahashi ,  Hiromi Matsuura ,  Yoshihisa Koyama ,  Masaya Muranaka ,  Katsutaka Kimura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Hidetoshi Iwai

发明人： Yasushi Takahashi ,  Hiromi Matsuura ,  Yoshihisa Koyama ,  Masaya Muranaka ,  Katsutaka Kimura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Hidetoshi Iwai

IPC分类号： H01L23/522 ,  H01L27/108

CPC分类号： H01L23/5226 ,  H01L27/10805 ,  H01L2924/0002 ,  Y10S257/923

摘要： A semiconductor integrated circuit device is provided which includes a memory cell array located in a generally central area of a semiconductor substrate with peripheral circuits located at both ends of the semiconductor substrate. A wiring layer is also provided which couples the peripheral circuits to one another. This wiring layer is arranged to have a double-layer structure of first and second aluminum layers which are electrically coupled to one another.

摘要翻译： 提供一种半导体集成电路器件，其包括位于半导体衬底的大致中心区域中的存储单元阵列，其具有位于半导体衬底两端的外围电路。 还提供了将外围电路彼此耦合的布线层。 该布线层被布置成具有彼此电耦合的第一和第二铝层的双层结构。

公开(公告)号：US5872734A

公开(公告)日：1999-02-16

申请号：US60364

申请日：1998-04-15

申请人： Toshihiro Tanaka ,  Masataka Kato ,  Katsutaka Kimura ,  Tetsuya Tsujikawa ,  Kazuyoshi Oshima ,  Kazuyuki Miyazawa

发明人： Toshihiro Tanaka ,  Masataka Kato ,  Katsutaka Kimura ,  Tetsuya Tsujikawa ,  Kazuyoshi Oshima ,  Kazuyuki Miyazawa

IPC分类号： G11C17/00 ,  G11C7/10 ,  G11C16/06 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC分类号： G11C7/103 ,  G11C16/26

摘要： A semiconductor nonvolatile memory device including transistors whose threshold voltages can be electrically rewritten (erased, written). A read-selected word line voltage Vrw, lower than the supply voltage Vcc applied from the outside, is applied, and the threshold voltage difference between the higher threshold voltage VthH and the lower threshold voltage VthL in the two states of nonvolatile memory cells is reduced to bring the higher threshold voltage VthH close to the lower threshold voltage VthL. Moreover, a threshold voltage Vthi in the thermally equilibrium state of the memory cell, corresponding to the two threshold voltages of the two states, is set between the higher threshold voltage VthH and the lower threshold voltage VthL.

摘要翻译： 一种包括晶体管的半导体非易失性存储器件，其阈值电压可被电刷写（擦除，写入）。 施加低于从外部施加的电源电压Vcc的读取选择字线电压Vrw，并且在非易失性存储单元的两种状态下的较高阈值电压VthH与较低阈值电压VthL之间的阈值电压差减小 以使较高的阈值电压VthH接近于较低的阈值电压VthL。 此外，与两个状态的两个阈值电压对应的存储单元的热平衡状态下的阈值电压Vthi设定在较高阈值电压VthH与下限阈值电压VthL之间。

公开(公告)号：US5748532A

公开(公告)日：1998-05-05

申请号：US677842

申请日：1996-07-10

申请人： Toshihiro Tanaka ,  Masataka Kato ,  Katsutaka Kimura ,  Tetsuya Tsujikawa ,  Kazuyoshi Oshima ,  Kazuyuki Miyazawa

发明人： Toshihiro Tanaka ,  Masataka Kato ,  Katsutaka Kimura ,  Tetsuya Tsujikawa ,  Kazuyoshi Oshima ,  Kazuyuki Miyazawa

IPC分类号： G11C17/00 ,  G11C7/10 ,  G11C16/06 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C7/103 ,  G11C16/26

摘要： A semiconductor nonvolatile memory device including transistors whose threshold voltages can be electrically rewritten (erased, written). A read-selected word line voltage Vrw, lower than the supply voltage Vcc applied from the outside, is applied, and the threshold voltage difference between the higher threshold voltage VthH and the lower threshold voltage VthL in the two states of the nonvolatile memory cells is reduced to bring the higher threshold voltage VthH close to the lower threshold voltage VthL. Moreover, a threshold voltage Vthi in the thermally equilibrium state of the memory cell, corresponding to the two threshold voltages of the two states, is set between the higher threshold voltage VthH and the lower threshold voltage VthL.

摘要翻译： 一种包括晶体管的半导体非易失性存储器件，其阈值电压可被电刷写（擦除，写入）。 施加低于从外部施加的电源电压Vcc的读取选择的字线电压Vrw，并且非易失性存储单元的两种状态下的较高阈值电压VthH与较低阈值电压VthL之间的阈值电压差为 减小以使较高的阈值电压VthH接近于较低的阈值电压VthL。 此外，与两个状态的两个阈值电压对应的存储单元的热平衡状态下的阈值电压Vthi设定在较高阈值电压VthH与下限阈值电压VthL之间。

公开(公告)号：US4916700A

公开(公告)日：1990-04-10

申请号：US156897

申请日：1988-02-17

申请人： Kazuya Ito ,  Katsutaka Kimura ,  Kazuyuki Miyazawa

发明人： Kazuya Ito ,  Katsutaka Kimura ,  Kazuyuki Miyazawa

IPC分类号： G11C29/00 ,  G11C11/401 ,  G11C29/34

CPC分类号： G11C29/34

摘要： A semiconductor storage device is disclosed which has a plurality of common data lines for delivering information from plural memory cells selected out of a plurality of memory cells during a normal operation mode, a plurality of amplifier circuits provided corresponding to the plurality of common data lines, a plurality of first testing logical circuits each one of which is provided for plural amplifier circuits which are disposed in close vicinity to each other of the plurality of amplifier circuits, and a second testing logical circuit for receiving each of output signals from the plurality of first testing logical circuits during the testing mode.

摘要翻译： 公开了一种半导体存储装置，其具有多个公共数据线，用于在正常操作模式期间从多个存储单元中选择的多个存储单元传送信息;对应于多个公共数据线提供的多个放大器电路， 多个第一测试逻辑电路，每个第一测试逻辑电路被设置用于多个放大器电路中的多个放大器电路，所述多个放大器电路被布置在所述多个放大器电路中彼此相邻;以及第二测试逻辑电路，用于接收来自所述多个第一 在测试模式下测试逻辑电路。