公开(公告)号：US5151772A

公开(公告)日：1992-09-29

申请号：US616705

申请日：1990-11-20

申请人： Yasushi Takahashi ,  Hiromi Matsuura ,  Yoshihisa Koyama ,  Masaya Muranaka ,  Katsutaka Kimura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Hidetoshi Iwai

发明人： Yasushi Takahashi ,  Hiromi Matsuura ,  Yoshihisa Koyama ,  Masaya Muranaka ,  Katsutaka Kimura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Hidetoshi Iwai

IPC分类号： H01L23/522 ,  H01L27/108

CPC分类号： H01L23/5226 ,  H01L27/10805 ,  H01L2924/0002 ,  Y10S257/923

摘要： A semiconductor integrated circuit device is provided which includes a memory cell array located in a generally central area of a semiconductor substrate with peripheral circuits located at both ends of the semiconductor substrate. A wiring layer is also provided which couples the peripheral circuits to one another. This wiring layer is arranged to have a double-layer structure of first and second aluminum layers which are electrically coupled to one another.

摘要翻译： 提供一种半导体集成电路器件，其包括位于半导体衬底的大致中心区域中的存储单元阵列，其具有位于半导体衬底两端的外围电路。 还提供了将外围电路彼此耦合的布线层。 该布线层被布置成具有彼此电耦合的第一和第二铝层的双层结构。

公开(公告)号：US5426613A

公开(公告)日：1995-06-20

申请号：US972907

申请日：1992-11-06

申请人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

发明人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C29/027 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1045 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/78

摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

摘要翻译： 提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。 结合这些，接合垫被布置在适于不同包装类型的最佳位置处。 还提供了各种布局布置以最小化空间并改善访问时间。 提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

公开(公告)号：US5217917A

公开(公告)日：1993-06-08

申请号：US496280

申请日：1990-03-20

申请人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takemuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

发明人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takemuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50

CPC分类号： G11C29/027 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1045 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/78

摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

摘要翻译： 提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。 结合这些，接合垫被布置在适于不同包装类型的最佳位置处。 还提供了各种布局布置以最小化空间并改善访问时间。 提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

公开(公告)号：US5805513A

公开(公告)日：1998-09-08

申请号：US432867

申请日：1995-05-02

申请人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

发明人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/027 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1045 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/78

摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

公开(公告)号：US5287000A

公开(公告)日：1994-02-15

申请号：US674969

申请日：1991-03-26

申请人： Yasushi Takahashi ,  Kazuyuki Miyazawa ,  Hidetoshi Iwai ,  Masaya Muranaka ,  Yoshitaka Kinoshita ,  Satoru Koshiba

发明人： Yasushi Takahashi ,  Kazuyuki Miyazawa ,  Hidetoshi Iwai ,  Masaya Muranaka ,  Yoshitaka Kinoshita ,  Satoru Koshiba

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L27/10 ,  H01L29/44 ,  H02G3/08

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/49541 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2224/49171 ,  H01L2224/49179 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011

摘要： According to one aspect of the present invention, a semiconductor chip, which can be mounted in a zigzag in-line type package (ZIP) partially using a tabless lead frame, includes bonding pads arranged on the chip so that the chip can be applied also to other different types of packages. These different types of packages include a small out-line J-bent type package (SOJ) which uses a lead frame with tab, and a dual in-line type package (DIP) which uses a tabless lead frame. Further, a plurality of bonding pad pairs are provided amongst the bonding pads on the chip, each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to make the semiconductor chip compatible with a variety of or different types of packages. In accordance with another aspect of the invention, a resin-encapsulated semiconductor device of the ZIP structure is provided in which a semiconductor pellet having a plurality of external terminals disposed on a device-forming surface along each side of the planar shape is encapsulated with a resin, wherein inner leads for signals connected electrically with external terminals, disposed opposing to the surface of the resin-encapsulated portion disposed with outer leads and disposed along the most remote side of the semiconductor pellet, are arranged so as to overlap the semiconductor pellet.

摘要翻译： 根据本发明的一个方面，可以使用无引线引线框架部分地以锯齿形的在线型封装（ZIP）安装的半导体芯片包括布置在芯片上的焊盘，使得芯片也可以被应用 到其他不同类型的包。 这些不同类型的封装包括使用带引脚的引线框架的小型外部J型弯曲型封装（SOJ）和使用无引脚引线框架的双列直插型封装（DIP）。 此外，在芯片上的接合焊盘之间设置多个接合焊盘对，这种接合焊盘对的每个焊盘具有与其相关联的另一个焊盘相同的功能，从而在半导体芯片上的不同接合焊盘中复制共同的功能，以便 使半导体芯片与各种或不同类型的封装兼容。 根据本发明的另一方面，提供了一种ZIP结构的树脂封装的半导体器件，其中具有设置在沿着平面形状的每一侧的器件形成表面上的多个外部端子的半导体芯片被封装在 树脂，其中与外部端子电连接的信号的内部引线设置成与设置有外部引线并沿着半导体芯片的最远侧设置的树脂封装部分的表面相对设置，以与半导体芯片重叠。

公开(公告)号：US4934820A

公开(公告)日：1990-06-19

申请号：US256862

申请日：1988-10-12

申请人： Yasushi Takahashi ,  Kazuyuki Miyazawa ,  Hidetoshi Iwai ,  Masaya Muranaka

发明人： Yasushi Takahashi ,  Kazuyuki Miyazawa ,  Hidetoshi Iwai ,  Masaya Muranaka

IPC分类号： H01L21/60 ,  G11C11/401 ,  H01L23/495 ,  H01L23/50

CPC分类号： H01L24/49 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49555 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011

摘要： According to the present invention, a semiconductor chip is mounted on a zigzag in-line type package (ZIP) partially using a tabless lead frame and bonding pads are arranged on the chip so that the chip can be applied also to other different types of packages. As different types of packages there are a small out-line J-bent type package (SOJ) for which there is used a lead frame with tab and a dual in-line type package (DIP) for which there is used a tabless lead frame. Further, a plurality of bonding pad pairs are provided among the bonding pads on the chip each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to readily facilitate, or make compatible, the semiconductor chip to a variety of or different types of packages.

摘要翻译： 根据本发明，半导体芯片部分地使用无引线引线框安装在Z字形在线型封装（ZIP）上，并且焊盘布置在芯片上，使得芯片也可以应用于其他不同类型的封装 。 作为不同类型的封装，有一个小型的外部J型弯曲型封装（SOJ），其中使用了带有引脚的引线框架和双列直插式封装（DIP），其中使用无引脚引线框架 。 此外，在芯片上的接合焊盘之间设置多个接合焊盘对，这样的焊盘对的每个焊盘具有与其相关的另一焊盘相同的功能，从而在半导体芯片上的不同接合焊盘中复制共同的功能，以便 容易地将半导体芯片促进或兼容到各种或不同类型的封装。

公开(公告)号：US5021998A

公开(公告)日：1991-06-04

申请号：US339843

申请日：1989-04-18

申请人： Yukihide Suzuki ,  Masaya Muranaka ,  Masamichi Ishihara

发明人： Yukihide Suzuki ,  Masaya Muranaka ,  Masamichi Ishihara

IPC分类号： G11C29/00 ,  G11C29/50 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10808

摘要： Disclosed are measurement (observation) pads for judging whether or not a dynamic random access memory (DRAM) adopting a shared sense system is functioning as designed. Concretely, measurement pads are formed by the step of forming a second layer of wiring respectively connected to pairs of complementary data lines which are formed by the step of forming a first layer of wiring, and the signal waveforms of the pairs of complementary data lines are measured using the measurement pads. Further, the measurement pads are provided between wiring layers which become fixed potentials in, at least, the operation of measuring data. In addition, each of the measurement pads is used in common by data lines which are respectively connected to two memory cells located in different memory cell mats.

摘要翻译： 公开了用于判断采用共享感测系统的动态随机存取存储器（DRAM）是否如此设计的功能的测量（观察）焊盘。 具体地，通过形成分别连接到形成第一层布线的步骤形成的互补数据线对的第二层布线的步骤形成测量焊盘，并且互补数据线对的信号波形是 使用测量垫测量。 此外，至少在测量数据的操作中，测量焊盘设置在成为固定电位的布线层之间。 此外，每个测量焊盘由分别连接到位于不同存储单元垫中的两个存储单元的数据线共同使用。

公开(公告)号：US4849939A

公开(公告)日：1989-07-18

申请号：US100752

申请日：1987-09-24

申请人： Masaya Muranaka ,  Hiromi Matsuura ,  Kanehide Kenmizaki ,  Osamu Okayama

发明人： Masaya Muranaka ,  Hiromi Matsuura ,  Kanehide Kenmizaki ,  Osamu Okayama

IPC分类号： G11C11/401 ,  G11C8/00 ,  G11C29/00 ,  G11C29/04 ,  G11C29/42

CPC分类号： G11C29/835 ,  G11C8/00

摘要： A semiconductor memory having a memory array, a first and a second selection line which are connected to a memory cell, and a selection means which selects either one of the selection lines. The selection means includes a selection circuit which optionally selects the first selection line or the second selection line when an address signal corresponding to the first selection line is aligned with a predetermined address signal.

摘要翻译： 具有连接到存储单元的存储器阵列，第一和第二选择线的半导体存储器以及选择选择线之一的选择装置。 选择装置包括选择电路，当与第一选择线对应的地址信号与预定的地址信号对准时，可选地选择第一选择线或第二选择线。

公开(公告)号：US5485425A

公开(公告)日：1996-01-16

申请号：US375727

申请日：1995-01-20

申请人： Hidetoshi Iwai ,  Masaya Muranaka ,  Takumi Nasu ,  Shunichi Sukegawa

发明人： Hidetoshi Iwai ,  Masaya Muranaka ,  Takumi Nasu ,  Shunichi Sukegawa

IPC分类号： G11C11/401 ,  G11C17/12 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C17/126 ,  G11C29/84

摘要： There is provided a semiconductor memory device having a redundant column. This memory device has a redundant column disposed in the direction of the Y-system address, a ROM accessed by using an X-system address, a Y-system address signal having a defective cell included in the cells therein being electrically written into the ROM, a comparator circuit for comparing a signal read out from this ROM with a Y-system address signal and outputting a coincidence signal upon coincidence, and a defect relieving circuit responsive to output of the coincidence signal from this comparator circuit to cause selection of the redundant column of Y system instead of the Y-system address selection device.

摘要翻译： 提供了具有冗余列的半导体存储器件。 该存储装置具有沿Y系统地址的方向设置的冗余列，通过使用X系统地址访问的ROM，其中包含在其中的单元中的具有缺陷单元的Y系统地址信号被电写入ROM 比较电路，用于将从该ROM读出的信号与Y系统地址信号进行比较，并且一致地输出一致信号，以及响应来自该比较器电路的符合信号的输出的缺陷消除电路，以选择冗余 Y系列的列，而不是Y系统地址选择设备。

公开(公告)号：US5596537A

公开(公告)日：1997-01-21

申请号：US275700

申请日：1994-07-14

申请人： Shunichi Sukegawa ,  Shiyuzo Shiozaki ,  Hiromi Matsuura ,  Masaya Muranaka

发明人： Shunichi Sukegawa ,  Shiyuzo Shiozaki ,  Hiromi Matsuura ,  Masaya Muranaka

IPC分类号： G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C7/00

CPC分类号： G11C29/46

摘要： A semiconductor device test circuit for inclusion on a semiconductor chip having a semiconductor device thereon, wherein a test mode with respect to the semiconductor device is not entered during normal use of the semiconductor device and the test mode can be entered without applying a voltage higher than the power supply voltage to an external terminal of the semiconductor device. The test circuit includes a decoder circuit which detects the matching of a first address input corresponding to a test mode, and a latch circuit which latches the signal indicating the matching of the first address input with a test mode. A second decoder circuit then detects the matching of a second address to the test mode, the second address being input when the matching signal for the first address has been latched. A second latch circuit latches the signal indicating the matching of the second address. A third address input is processed by a third decoder circuit and a third latch circuit in the same way. This means that when a plurality of addresses (three addresses in the described example) which are consecutively input to the respective decoder circuits are in a predetermined, specific combination, a test enable signal is output and the test mode is activated.

摘要翻译： 一种用于包含在其上具有半导体器件的半导体芯片上的半导体器件测试电路，其中在半导体器件的正常使用期间不进入相对于半导体器件的测试模式，并且可以进入测试模式而不施加高于 对半导体器件的外部端子的电源电压。 测试电路包括检测与测试模式相对应的第一地址输入的匹配的解码器电路和锁存指示第一地址输入与测试模式匹配的信号的锁存电路。 第二解码器电路然后检测第二地址与测试模式的匹配，当第一地址的匹配信号被锁存时，第二地址被输入。 第二锁存电路锁存指示第二地址匹配的信号。 第三地址输入由第三解码器电路和第三锁存电路以相同的方式处理。 这意味着当连续输入到各个解码器电路的多个地址（所述示例中的三个地址）处于预定的特定组合时，输出测试使能信号并且测试模式被激活。