公开(公告)号：US07550790B2

公开(公告)日：2009-06-23

申请号：US11709072

申请日：2007-02-22

申请人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

发明人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

IPC分类号： H01L29/74

CPC分类号： H01L27/1214 ,  G09G3/20 ,  G09G3/2011 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0297 ,  H01L21/84 ,  H01L29/04 ,  H03K17/6872 ,  H03K17/693 ,  H03M1/682 ,  H03M1/765

摘要： A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

公开(公告)号：US06738005B2

公开(公告)日：2004-05-18

申请号：US10053656

申请日：2002-01-24

申请人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

发明人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

IPC分类号： H03M166

CPC分类号： H01L27/1214 ,  G09G3/20 ,  G09G3/2011 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0297 ,  H01L21/84 ,  H01L29/04 ,  H03K17/6872 ,  H03K17/693 ,  H03M1/682 ,  H03M1/765

摘要： A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

摘要翻译： 提供具有小面积的D / A转换电路。 在D / A转换电路中，根据从地址解码器的地址线发送的数字信号，选择四个灰度电压线中的一个。 包括两个N沟道TFT的电路串联连接到包括两个P沟道TFT的电路，并且包括彼此串联连接的电路的电路并联连接到每个灰度电压线。 此外，包括两个N沟道TFT的电路和包括两个P沟道TFT的电路的布置对于每个灰度电压线都是反向的。 由此，D / A转换电路中的布线的交叉变小，可以使面积变小。

公开(公告)号：US20050219098A1

公开(公告)日：2005-10-06

申请号：US11128333

申请日：2005-05-13

申请人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

发明人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

IPC分类号： G09G3/36 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H03K17/687 ,  H03K17/693 ,  H03M1/66 ,  H03M1/68 ,  H03M1/76

CPC分类号： H01L27/1214 ,  G09G3/20 ,  G09G3/2011 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0297 ,  H01L21/84 ,  H01L29/04 ,  H03K17/6872 ,  H03K17/693 ,  H03M1/682 ,  H03M1/765

摘要： A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

公开(公告)号：US20070158689A1

公开(公告)日：2007-07-12

申请号：US11709072

申请日：2007-02-22

申请人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

发明人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

IPC分类号： H01L27/10

CPC分类号： H01L27/1214 ,  G09G3/20 ,  G09G3/2011 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0297 ,  H01L21/84 ,  H01L29/04 ,  H03K17/6872 ,  H03K17/693 ,  H03M1/682 ,  H03M1/765

摘要： A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

公开(公告)号：US07184017B2

公开(公告)日：2007-02-27

申请号：US11128333

申请日：2005-05-13

申请人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

发明人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

IPC分类号： G09G3/36

CPC分类号： H01L27/1214 ,  G09G3/20 ,  G09G3/2011 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0297 ,  H01L21/84 ,  H01L29/04 ,  H03K17/6872 ,  H03K17/693 ,  H03M1/682 ,  H03M1/765

摘要： A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

摘要翻译： 提供具有小面积的D / A转换电路。 在D / A转换电路中，根据从地址解码器的地址线发送的数字信号，选择四个灰度电压线中的一个。 包括两个N沟道TFT的电路串联连接到包括两个P沟道TFT的电路，并且包括彼此串联连接的电路的电路并联连接到每个灰度电压线。 此外，包括两个N沟道TFT的电路和包括两个P沟道TFT的电路的布置对于每个灰度电压线都是反向的。 由此，D / A转换电路中的布线的交叉变小，可以使面积变小。

公开(公告)号：US06911926B2

公开(公告)日：2005-06-28

申请号：US10810573

申请日：2004-03-29

申请人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

发明人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

IPC分类号： G09G3/36 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H03K17/687 ,  H03K17/693 ,  H03M1/66 ,  H03M1/68 ,  H03M1/76 ,  H03M1/00

CPC分类号： H01L27/1214 ,  G09G3/20 ,  G09G3/2011 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0297 ,  H01L21/84 ,  H01L29/04 ,  H03K17/6872 ,  H03K17/693 ,  H03M1/682 ,  H03M1/765

摘要： A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

摘要翻译： 提供具有小面积的D / A转换电路。 在D / A转换电路中，根据从地址解码器的地址线发送的数字信号，选择四个灰度电压线中的一个。 包括两个N沟道TFT的电路串联连接到包括两个P沟道TFT的电路，并且包括彼此串联连接的电路的电路并联连接到每个灰度电压线。 此外，包括两个N沟道TFT的电路和包括两个P沟道TFT的电路的布置对于每个灰度电压线都是反向的。 由此，D / A转换电路中的布线的交叉变小，可以使面积变小。

公开(公告)号：US06441758B1

公开(公告)日：2002-08-27

申请号：US09197766

申请日：1998-11-23

申请人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

发明人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

IPC分类号： H03M100

CPC分类号： H01L27/1214 ,  G09G3/20 ,  G09G3/2011 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0297 ,  H01L21/84 ,  H01L29/04 ,  H03K17/6872 ,  H03K17/693 ,  H03M1/682 ,  H03M1/765

摘要： A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

摘要翻译： 提供具有小面积的D / A转换电路。 在D / A转换电路中，根据从地址解码器的地址线发送的数字信号，选择四个灰度电压线中的一个。 包括两个N沟道TFT的电路串联连接到包括两个P沟道TFT的电路，并且包括彼此串联连接的电路的电路并联连接到每个灰度电压线。 此外，包括两个N沟道TFT的电路和包括两个P沟道TFT的电路的布置对于每个灰度电压线都是反向的。 由此，D / A转换电路中的布线的交叉变小，可以使面积变小。