公开(公告)号：US20130145190A1

公开(公告)日：2013-06-06

申请号：US13816479

申请日：2010-08-26

申请人： Mamoru Sakugawa ,  Masamichi Fujito ,  Jun Setogawa ,  Masaru Takahashi ,  Shinsuke Yoshimura

发明人： Mamoru Sakugawa ,  Masamichi Fujito ,  Jun Setogawa ,  Masaru Takahashi ,  Shinsuke Yoshimura

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A central processing unit sets which of the following modes a data processing device is to operate in accordance with a user program. The high-speed operation mode allows operation within a first range in which an external supply voltage is relatively high. The wide voltage range operation mode allows operation within a second range in which the external supply voltage includes the first range and a relatively low voltage range, and an upper limit of a frequency of the first clock in the wide voltage range operation mode is lower than an upper limit of a frequency of the first clock in the high-speed operation mode. The frequency of the first clock in the low power consumption operation mode is lower than the frequency of the first clock in the high-speed operation mode and the frequency of the first clock in the wide voltage range operation mode.

摘要翻译： 中央处理单元根据用户程序设置数据处理装置要操作的以下哪种模式。 高速运行模式允许在外部电源电压相对较高的第一范围内运行。 宽电压范围操作模式允许在外部电源电压包括第一范围和相对低的电压范围的第二范围内操作，并且宽电压范围操作模式中的第一时钟的频率的上限低于 在高速运行模式中的第一时钟的频率的上限。 在低功耗操作模式中，第一时钟的频率低于高速操作模式中的第一时钟的频率和宽电压范围操作模式下的第一时钟的频率。

公开(公告)号：US20120002498A1

公开(公告)日：2012-01-05

申请号：US13171849

申请日：2011-06-29

申请人： Toru Matsushita ,  Ken Matsubara ,  Takashi Iwase ,  Hidenori Mitani ,  Jun Setogawa ,  Fumiko Yamada

发明人： Toru Matsushita ,  Ken Matsubara ,  Takashi Iwase ,  Hidenori Mitani ,  Jun Setogawa ,  Fumiko Yamada

IPC分类号： G11C5/14

CPC分类号： G11C5/145 ,  G11C16/30

摘要： Operational stability of the nonvolatile memory in plural power supply voltage modes set up in advance corresponding to the power supply voltage level is realized. A nonvolatile memory is configured with a memory array, a charge pump, a distributor for selecting an output voltage of the charge pump, and a sequencer for controlling operation of the charge pump and the distributor. The nonvolatile memory is also provided with an analyzer which notifies the sequencer of a power supply voltage mode selectively specified among plural power supply voltage modes set up in advance corresponding to power supply voltage levels, and which detects mismatch between the power supply voltage mode notified to the sequencer and an actually supplied power supply voltage and limits the operation of the charge pump and the distributor with the use of the sequencer, based on the detection result. Accordingly, operational stability of the nonvolatile memory is realized.

摘要翻译： 实现了与电源电压电平相对应地设置的多个电源电压模式中的非易失性存储器的操作稳定性。 非易失性存储器配置有存储器阵列，电荷泵，用于选择电荷泵的输出电压的分配器，以及用于控制电荷泵和分配器的操作的定序器。 非易失性存储器还设置有分析器，其向定序器通知在与电源电压电平相对应地设置的多个电源电压模式中选择性地指定的电源电压模式，并且检测通知给 定序器和实际提供的电源电压，并且基于检测结果限制使用定序器的电荷泵和分配器的操作。 因此，实现了非易失性存储器的操作稳定性。

公开(公告)号：US20050243643A1

公开(公告)日：2005-11-03

申请号：US11174472

申请日：2005-07-06

申请人： Jun Setogawa

发明人： Jun Setogawa

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  G11C8/00

CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076

摘要： A control circuit in a semiconductor memory device accessing a memory cell for a plurality of cycles includes an internal command generating circuit and a mask signal generating circuit. Upon receiving a control command, the internal command generating circuit outputs an internal signal instructing an operation to access the memory cell at H level when a mask signal is at L level, while outputs an internal signal at L level when the mask signal is at H level, because a latch circuit is reset. The mask signal generating circuit outputs the mask signal at H level for a following cycle, when the internal signal is output at H level.

摘要翻译： 在多个周期中访问存储单元的半导体存储器件中的控制电路包括内部指令产生电路和屏蔽信号发生电路。 当接收到控制命令时，当屏蔽信号为L电平时，内部指令产生电路输出指示进入H电平的存储单元的操作的内部信号，而当屏蔽信号为H时，输出内部信号为L电平 电平，因为锁存电路被复位。 当内部信号以H电平输出时，屏蔽信号发生电路输出H电平的屏蔽信号，用于随后的周期。

公开(公告)号：US6055210A

公开(公告)日：2000-04-25

申请号：US245085

申请日：1999-02-05

申请人： Jun Setogawa

发明人： Jun Setogawa

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  G11C8/00

CPC分类号： G11C7/1051 ,  G11C11/4076 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22

摘要： When the frequency of an external clock signal is higher than a prescribed frequency in an SDRAM, an output signal from a clock frequency detection circuit is at an L level, a transfer control signal is fixed to an H level, and first and second data buses are coupled together. Thus, a malfunction when the transfer control signal attains an H level in a pulse manner while read data is not output to the first data bus can be prevented. Accordingly, an SDRAM having a larger operating frequency range can be obtained.

摘要翻译： 当外部时钟信号的频率高于SDRAM中的规定频率时，来自时钟频率检测电路的输出信号为L电平，传输控制信号固定为H电平，第一和第二数据总线 耦合在一起。 因此，可以防止在不向第一数据总线输出读取数据时传送控制信号以脉冲方式达到H电平的故障。 因此，可以获得具有较大工作频率范围的SDRAM。

公开(公告)号：US06606274B2

公开(公告)日：2003-08-12

申请号：US10036512

申请日：2002-01-07

申请人： Tsukasa Ooishi ,  Jun Setogawa

发明人： Tsukasa Ooishi ,  Jun Setogawa

IPC分类号： G11C514

CPC分类号： G11C11/4074 ,  G11C5/143 ,  G11C5/147

摘要： The inventive semiconductor memory device comprises a synchronous circuit formed by a PLL circuit requiring precise operations, an internal circuit group and a VDC circuit. The VDC circuit, a capacitor, a PMOS transistor for a dummy current and an NMOS transistor serving as a high impedance element are arranged for the synchronous circuit. The VDC circuit is arranged for the internal circuit group. The VDC circuit eliminates power supply noise. The PMOS transistor stabilizes the operation of a differential amplifier of the VDC circuit. The capacitor keeps potential difference between a power supply side and a GND side constant. The NMOS transistor stabilizes the voltage on the GND side.

公开(公告)号：US06343035B1

公开(公告)日：2002-01-29

申请号：US09708607

申请日：2000-11-09

申请人： Takashi Kubo ,  Jun Setogawa ,  Takeshi Hamamoto

发明人： Takashi Kubo ,  Jun Setogawa ,  Takeshi Hamamoto

IPC分类号： G11C700

CPC分类号： G11C7/1006

摘要： When a first data bus line and a second data bus line as a pair are used as a complementary bus, a complementary data signal ZDATA1 is provided to the second data bus line, and an output buffer circuit that becomes unnecessary is rendered inactive. On the other hand, when the first and second data bus lines are used as two single data buses, a differential amplifier transmits two data signals without amplification to the first and second data bus lines. A data signal DATA2 is provided to the second data bus line. The output buffer circuit is activated, and a data signal ZDATA2 is output from an output node.

摘要翻译： 当作为一对的第一数据总线和第二数据总线作为互补总线时，互补数据信号ZDATA1被提供给第二数据总线，而不需要的输出缓冲电路变为无效。 另一方面，当第一和第二数据总线用作两个单个数据总线时，差分放大器将第二和第二数据总线不经放大地发送两个数据信号。 数据信号DATA2被提供给第二数据总线。 输出缓冲电路被激活，从输出节点输出数据信号ZDATA2。

公开(公告)号：US07630239B2

公开(公告)日：2009-12-08

申请号：US11898376

申请日：2007-09-11

申请人： Minoru Senda ,  Jun Setogawa

发明人： Minoru Senda ,  Jun Setogawa

IPC分类号： G11C11/34

CPC分类号： G11C16/3436

摘要： The present invention provides a semiconductor device which comprises a plurality of memory cells which stores data therein based on threshold voltages thereof, a plurality of bit lines on which read signals based on the stored data of the memory cells appear respectively, a plurality of sense amplifiers which are respectively disposed corresponding to the bit lines and which respectively detect the read signals having appeared on the bit lines and output first and second signals respectively having logical levels different from one another from first and second nodes, based on the detected read signals, and a determination unit which determines, based on the first and second signals received from the first and second nodes of the sense amplifiers, whether the threshold voltages of the memory cells are normal.

摘要翻译： 本发明提供了一种半导体器件，其包括多个存储器单元，其基于其阈值电压存储数据，多个位线，基于存储单元的存储数据的读取信号分别出现在多个位线上，多个读出放大器 其分别对应于位线布置，并且分别检测出现在位线上的读取信号，并且基于检测到的读取信号输出分别具有彼此不同于第一和第二节点的逻辑电平的第一和第二信号，以及 确定单元，其基于从读出放大器的第一和第二节点接收的第一和第二信号来确定存储器单元的阈值电压是否正常。

公开(公告)号：US07092314B2

公开(公告)日：2006-08-15

申请号：US11174472

申请日：2005-07-06

申请人： Jun Setogawa

发明人： Jun Setogawa

IPC分类号： G11C8/00

CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076

摘要： A control circuit in a semiconductor memory device accessing a memory cell for a plurality of cycles includes an internal command generating circuit and a mask signal generating circuit. Upon receiving a control command, the internal command generating circuit outputs an internal signal instructing an operation to access the memory cell at H level when a mask signal is at L level, while outputs an internal signal at L level when the mask signal is at H level, because a latch circuit is reset. The mask signal generating circuit outputs the mask signal at H level for a following cycle, when the internal signal is output at H level.

摘要翻译： 在多个周期中访问存储单元的半导体存储器件中的控制电路包括内部指令产生电路和屏蔽信号发生电路。 当接收到控制命令时，当屏蔽信号为L电平时，内部指令产生电路输出指示进入H电平的存储单元的操作的内部信号，而当屏蔽信号为H时，输出内部信号为L电平 电平，因为锁存电路被复位。 当内部信号以H电平输出时，屏蔽信号发生电路输出H电平的屏蔽信号，用于随后的周期。

公开(公告)号：US06400643B1

公开(公告)日：2002-06-04

申请号：US09796537

申请日：2001-03-02

申请人： Jun Setogawa

发明人： Jun Setogawa

IPC分类号： G11C800

CPC分类号： G06F1/32

摘要： An internal clock signal generating circuit includes a phase comparing circuit which is made active in accordance with a control signal SEN which becomes intermittently active in a power down mode from an operation permission signal generating circuit, receives an external clock signal and an output from a delay circuit, and compares phases of the signal and the output with each other, an address generating circuit for receiving a phase comparison result and generating a delay amount control signal for controlling a delay amount, and an address decoder for receiving an output of the delay circuit and generating a decode signal for controlling the delay amount.

摘要翻译： 内部时钟信号发生电路包括相位比较电路，该相位比较电路根据从动作允许信号发生电路在断电模式中间歇地起作用的控制信号SEN而被激活，接收外部时钟信号和延迟的输出 电路，并且将信号和输出的相位彼此比较，地址发生电路，用于接收相位比较结果并产生用于控制延迟量的延迟量控制信号;以及地址解码器，用于接收延迟电路的输出 并产生用于控制延迟量的解码信号。

公开(公告)号：US06337828B2

公开(公告)日：2002-01-08

申请号：US09764134

申请日：2001-01-19

申请人： Tsukasa Ooishi ,  Jun Setogawa

发明人： Tsukasa Ooishi ,  Jun Setogawa

IPC分类号： G11C514

CPC分类号： G11C11/4074 ,  G11C5/143 ,  G11C5/147

摘要： The inventive semiconductor memory device comprises a synchronous circuit formed by a PLL circuit requiring precise operations, an internal circuit group and a VDC circuit. The VDC circuit, a capacitor, a PMOS transistor for a dummy current and an NMOS transistor serving as a high impedance element are arranged for the synchronous circuit. The VDC circuit is arranged for the internal circuit group. The VDC circuit eliminates power supply noise. The PMOS transistor stabilizes the operation of a differential amplifier of the VDC circuit. The capacitor keeps potential difference between a power supply side and a GND side constant. The NMOS transistor stabilizes the voltage on the GND side.

摘要翻译： 本发明的半导体存储器件包括由需要精确操作的PLL电路，内部电路组和VDC电路形成的同步电路。 VDC电路，电容器，用于虚拟电流的PMOS晶体管和用作高阻抗元件的NMOS晶体管被布置用于同步电路。 VDC电路用于内部电路组。 VDC电路消除了电源噪声。 PMOS晶体管稳定了VDC电路的差分放大器的工作。 电容器保持电源侧和GND侧之间的电位差恒定。 NMOS晶体管稳定GND侧的电压。