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    Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon
    3.
    发明授权
    Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon 有权
    在其上形成具有应力诱导侧壁绝缘间隔物的场效应晶体管的方法

    公开(公告)号：US07923365B2

    公开(公告)日：2011-04-12

    申请号：US11874118

    申请日：2007-10-17

    申请人： Jun-jung Kim ,  Sang-jine Park ,  Min-ho Lee ,  Thomas W. Dyer ,  Sunfei Fang ,  O-sung Kwon ,  Johnny Widodo

    发明人： Jun-jung Kim ,  Sang-jine Park ,  Min-ho Lee ,  Thomas W. Dyer ,  Sunfei Fang ,  O-sung Kwon ,  Johnny Widodo

    IPC分类号： H01L21/8234 ,  H01L21/336

    CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

    摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.

    摘要翻译： 形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。 当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。 然后从栅电极的侧壁去除牺牲隔离物。 然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管） 。

    Field Effect Transistors Having Gate Electrode Silicide Layers with Reduced Surface Damage
    4.
    发明申请
    Field Effect Transistors Having Gate Electrode Silicide Layers with Reduced Surface Damage 审中-公开
    具有栅电极的场效应晶体管具有降低的表面损伤的硅化物层

    公开(公告)号：US20110156110A1

    公开(公告)日：2011-06-30

    申请号：US13043059

    申请日：2011-03-08

    申请人： Jun-jung Kim ,  Sang-jine Park ,  Min-ho Lee ,  Thomas W. Dyer ,  Sunfei Fang ,  O-sung Kwon ,  Johnny Widodo

    发明人： Jun-jung Kim ,  Sang-jine Park ,  Min-ho Lee ,  Thomas W. Dyer ,  Sunfei Fang ,  O-sung Kwon ,  Johnny Widodo

    IPC分类号： H01L29/772

    CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

    摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.

    摘要翻译： 形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。 当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。 然后从栅电极的侧壁去除牺牲隔离物。 然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管） 。

    Methods of Forming Integrated Circuit Devices Having Ion-Cured Electrically Insulating Layers Therein
    6.
    发明申请
    Methods of Forming Integrated Circuit Devices Having Ion-Cured Electrically Insulating Layers Therein 有权
    形成具有离子固化电绝缘层的集成电路器件的方法

    公开(公告)号：US20090098706A1

    公开(公告)日：2009-04-16

    申请号：US11871602

    申请日：2007-10-12

    申请人： Jun-jung Kim ,  Joo-chan Kim ,  Jae-eon Park ,  Richard Anthony Conti ,  Zhao Lun ,  Johnny Widodo ,  William C. Wille ,  Biao Zuo

    发明人： Jun-jung Kim ,  Joo-chan Kim ,  Jae-eon Park ,  Richard Anthony Conti ,  Zhao Lun ,  Johnny Widodo ,  William C. Wille ,  Biao Zuo

    IPC分类号： H01L21/762

    CPC分类号： H01L21/3105 ,  H01L21/76229 ,  H01L21/76232

    摘要： Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.

    摘要翻译： 形成集成电路器件的方法包括在半导体衬底的表面中形成沟槽，并用其中具有接缝的电绝缘区填充沟槽。 可以通过在沟槽的侧壁和底部上沉积足够厚的电绝缘层来填充沟槽。 然后将固化离子以足够的能量和剂量注入电绝缘区域以减少其中原子序列的程度。 固化离子可以是选自氮（N），磷（P），硼（B），砷（As），碳（C），氩（Ar），锗（Ge），氦 ），氖（Ne）和氙（Xe）。 这些固化离子可以以至少约80KeV的能量和至少约5×1014个离子/ cm 2的剂量注入。 然后将电绝缘区域在足够的温度下退火并持续足够的时间以增加电绝缘区域内的原子级数。

    Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein
    7.
    发明授权
    Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein 有权
    形成其中具有离子固化的电绝缘层的集成电路器件的方法

    公开(公告)号：US07838390B2

    公开(公告)日：2010-11-23

    申请号：US11871602

    申请日：2007-10-12

    申请人： Jun-jung Kim ,  Joo-chan Kim ,  Jae-eon Park ,  Richard Anthony Conti ,  Zhao Lun ,  Johnny Widodo ,  William C. Wille ,  Biao Zuo

    发明人： Jun-jung Kim ,  Joo-chan Kim ,  Jae-eon Park ,  Richard Anthony Conti ,  Zhao Lun ,  Johnny Widodo ,  William C. Wille ,  Biao Zuo

    IPC分类号： H01L21/76

    CPC分类号： H01L21/3105 ,  H01L21/76229 ,  H01L21/76232

    摘要： Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.

    摘要翻译： 形成集成电路器件的方法包括在半导体衬底的表面中形成沟槽，并用其中具有接缝的电绝缘区填充沟槽。 可以通过在沟槽的侧壁和底部上沉积足够厚的电绝缘层来填充沟槽。 然后将固化离子以足够的能量和剂量注入电绝缘区域以减少其中原子序列的程度。 固化离子可以是选自氮（N），磷（P），硼（B），砷（As），碳（C），氩（Ar），锗（Ge），氦 ），氖（Ne）和氙（Xe）。 这些固化离子可以以至少约80KeV的能量和至少约5×10 14离子/ cm 2的剂量注入。 然后将电绝缘区域在足够的温度下退火并持续足够的时间以增加电绝缘区域内的原子级数。