公开(公告)号：US20080062787A1

公开(公告)日：2008-03-13

申请号：US11777627

申请日：2007-07-13

Applicant: Jung-Hwa LEE ,  Ji-Hyun LEE

Inventor： Jung-Hwa LEE ,  Ji-Hyun LEE

IPC: G11C29/02

CPC classification number: G11C29/02 ,  G11C11/401 ,  G11C29/025 ,  G11C29/12005 ,  G11C2029/1204

Abstract: Provided is a bit line bridge detection method for selectively floating even-numbered or odd-numbered bit lines. The bit line bridge detection method simultaneously activates even-numbered sense amplifiers and odd-numbered sense amplifiers in response to a sense amplifier enable signal. The even-numbered sense amplifiers and the odd-numbered sense amplifiers are selectively disabled in response to a sense amplifier disable signal generated at a predetermined time after the sense amplifier enable signal is generated, and an even-numbered or odd-numbered sense amplifier selection signal which is stored in a mode register. As a result, the even-numbered bit lines and the odd-numbered bit lines are selectively floated. If data input to memory cells is inverted, a bit line bridge is detected.

Abstract translation: 提供了用于选择性地浮置偶数位或奇数位线的位线桥检测方法。 位线桥检测方法响应于读出放大器使能信号同时激活偶数读出放大器和奇数读出放大器。 响应于在产生读出放大器使能信号之后的预定时间产生的读出放大器禁止信号，选择性地禁止偶数读出放大器和奇数读出放大器，以及偶数或奇数读出放大器选择 信号存储在模式寄存器中。 结果，偶数位线和奇数位线被选择性浮动。 如果输入到存储单元的数据被反转，则检测位线桥。

公开(公告)号：US20120045284A1

公开(公告)日：2012-02-23

申请号：US12940385

申请日：2010-11-05

Applicant: Jae-Gon KIM ,  Jung-Hwa LEE ,  Yong-Chan CHO ,  Joo-Sung AHN ,  Choon-Oh LEE ,  Ho-Cheol SONG

Inventor： Jae-Gon KIM ,  Jung-Hwa LEE ,  Yong-Chan CHO ,  Joo-Sung AHN ,  Choon-Oh LEE ,  Ho-Cheol SONG

IPC: B09C1/08

CPC classification number: B09C1/02 ,  B09C1/08

Abstract: Provided is a method for remediating arsenic-contaminated soil, including: a collection step of collecting arsenic-contaminated soil; a washing step of adding the collected soil to a washing solution, which is acidic in nature and provides reducing conditions to the soil, so as to remove arsenic from the soil and transfer the removed arsenic to the washing solution; a solid-liquid separation step of separating the soil and the washing solution from each other after the washing step; and a post-treatment step of removing arsenic from the washing solution, which was separated in the solid-liquid separation step, and employing the soil for remediation.

Abstract translation: 提供了一种补救砷污染土壤的方法，包括：收集砷污染土壤的收集步骤; 将收集的土壤添加到本质上是酸性并为土壤提供还原条件的洗涤溶液的洗涤步骤，以从土壤中除去砷并将去除的砷转移到洗涤溶液中; 在洗涤步骤之后将污物和洗涤液彼此分离的固液分离步骤; 以及从固液分离工序中分离的洗涤液中除去砷的后处理工序，并使用土壤进行修复。

公开(公告)号：US20110075499A1

公开(公告)日：2011-03-31

申请号：US12894246

申请日：2010-09-30

Applicant: Jae-Young LEE ,  Jung-Hwa LEE ,  Bong-Jin KANG

Inventor： Jae-Young LEE ,  Jung-Hwa LEE ,  Bong-Jin KANG

IPC: G11C7/06

CPC classification number: G11C11/4091 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

Abstract: A semiconductor memory device comprises a substrate comprising a first cell array region, a first sense circuit region, a second sense circuit region, and a second cell array region that are arranged in order from a first side to a second side. First and second bit lines are coupled to a plurality of memory cells in the first cell array region, and first and second complementary bit lines are coupled to a plurality of memory cells in the second cell array region. A first column selector is formed in the first sense circuit region and is coupled to the first bit line and the first complementary bit line. A second column selector is formed in the second sense circuit region and is coupled to the second bit line and the second complementary bit line. The first column selector and the second column selector are formed directly adjacent to each other.

Abstract translation: 一种半导体存储器件，包括一个衬底，该衬底包括从第一侧到第二侧依次布置的第一单元阵列区，第一感测电路区，第二感测电路区和第二单元阵列区。 第一和第二位线耦合到第一单元阵列区域中的多个存储单元，并且第一和第二互补位线耦合到第二单元阵列区域中的多个存储单元。 第一列选择器形成在第一感测电路区域中，并且耦合到第一位线和第一互补位线。 第二列选择器形成在第二感测电路区域中，并且耦合到第二位线和第二互补位线。 第一列选择器和第二列选择器彼此直接相邻地形成。

公开(公告)号：US20080068069A1

公开(公告)日：2008-03-20

申请号：US11858071

申请日：2007-09-19

Applicant: Dong-Myung EUN ,  Jung-Hwa LEE

Inventor： Dong-Myung EUN ,  Jung-Hwa LEE

IPC: G05F1/10

CPC classification number: H02M3/07

Abstract: A high voltage generator is provided. The high voltage generator may comprise a high voltage output node, a plurality of pumping stages, a plurality of charge transfer elements, and a field relieving unit. The plurality of pumping stages sequentially pump charges in response to a sequentially enabled plurality of pump signals and output the pumped charges, respectively. The plurality of charge transfer elements sequentially transfer the charges sequentially pumped by the plurality of pumping stages to the next pumping stage and transfer the charge of an output node of the last pumping stage to the high voltage output node. The field relieving unit reduces the voltage of the input terminal of at least one of the plurality of charge transfer elements. The high voltage generator reduces hot carrier injection in charge transfer transistors without decreasing pumping efficiency.

Abstract translation: 提供高压发生器。 高压发生器可以包括高压输出节点，多个泵送级，多个电荷转移元件和场释放单元。 多个泵送阶段响应于顺序启用的多个泵浦信号顺序地泵送电荷并分别输出泵送的电荷。 多个电荷转移元件顺序地将由多个泵送阶段泵浦的电荷转移到下一个泵送级，并将最后一个泵浦级的输出节点的电荷传送到高电压输出节点。 场释放单元降低多个电荷转移元件中的至少一个的输入端子的电压。 高压发生器减少电荷转移晶体管中的热载流子注入，而不会降低泵送效率。

公开(公告)号：US20110176873A1

公开(公告)日：2011-07-21

申请号：US12756739

申请日：2010-04-08

Applicant: Jae-Gon KIM ,  Jung-Hwa LEE ,  Young-Woo CHOI ,  Yong-Chan CHO

Inventor： Jae-Gon KIM ,  Jung-Hwa LEE ,  Young-Woo CHOI ,  Yong-Chan CHO

IPC: B09C1/08

CPC classification number: B09C1/02 ,  B09C1/08

Abstract: Provided is a method of remediating cyanide-contaminated soil. The method is provided to remediate soil contaminated with cyanide and treat the cyanide, which includes collecting the soil contaminated with first cyanide in a solid state and second cyanide in a gaseous or dissolved state, dissociating cyanide by mixing the soil with an alkali washing solution, dissolving the first cyanide in a solid state in the washing solution, and transferring the second cyanide in a dissolved state dissociated from the soil to the washing solution, dissociating the soil from the washing solution, precipitating the first cyanide in a solid state by acidifying the washing solution containing the cyanide, and performing post-treatment on the first cyanide after the first cyanide precipitated in a solid state is dissociated from the washing solution.

Abstract translation: 提供了一种补救氰化物污染土壤的方法。 该方法用于修复被氰化物污染的污染物并处理氰化物，其中包括以固体状态收集被第一氰化物污染的土壤，并以气态或溶解状态收集第二氰化物，通过将土壤与碱性洗涤溶液混合来解离氰化物， 将第一氰化物以固态溶解在洗涤溶液中，并将从土壤中分解的溶解状态的第二氰化物转移到洗涤溶液中，使污物从洗涤溶液中解离，将固体状态的第一氰化物沉淀， 含有氰化物的洗涤溶液，并且在固体中沉淀出的第一氰化物后，在第一氰化物上进行后处理从洗涤溶液中解离。

公开(公告)号：US20100091589A1

公开(公告)日：2010-04-15

申请号：US12577816

申请日：2009-10-13

Applicant: Jung-Hwa LEE

Inventor： Jung-Hwa LEE

IPC: G11C7/00 ,  G11C8/08

CPC classification number: G11C7/18 ,  G11C7/1042 ,  G11C7/12 ,  G11C8/08

Abstract: A semiconductor memory device includes a memory block having first and second word lines extending in a first direction and bit lines extending in a perpendicular second direction; a first driver region at a side of the memory block in the first direction driving the first word lines; a second driver region at another side of the memory block in the first direction driving the second word lines; a sensing region at a side of the memory block in the second direction controlling the bit lines responsive to signals from drive lines; a first conjunction region at an intersection of the first driver and sensing regions including a first driver driving the drive lines responsive to signals from control lines; and a second conjunction region at an intersection of the second driver and sensing regions, including a second driver driving the drive lines responsive to signals from the control lines.

Abstract translation: 半导体存储器件包括具有沿第一方向延伸的第一和第二字线的存储块和沿垂直第二方向延伸的位线; 驱动所述第一字线的所述第一方向的所述存储器块的一侧的第一驱动器区域; 在所述第一方向上的所述存储块的另一侧的第二驱动器区域驱动所述第二字线; 响应于来自驱动线的信号，沿所述第二方向在所述存储器块的一侧的感测区域控制所述位线; 响应于来自控制线的信号，第一驱动器和检测区域的交叉点处的第一连接区域包括驱动驱动线路的第一驱动器; 以及在第二驱动器和感测区域的交叉点处的第二连接区域，包括响应于来自控制线路的信号驱动驱动线路的第二驱动器。

公开(公告)号：US20090065837A1

公开(公告)日：2009-03-12

申请号：US12264490

申请日：2008-11-04

Applicant: Jung-Hwa LEE ,  Si-Woo LEE

Inventor： Jung-Hwa LEE ,  Si-Woo LEE

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/0207 ,  H01L27/0629 ,  H01L28/40

Abstract: Provided is a semiconductor memory device having peripheral circuit capacitors. In the semiconductor memory device, a first node is electrically connected to a plurality of lower electrodes of a plurality of capacitors in a peripheral circuit region to connect at least a portion of the capacitors in parallel. A second node is electrically connected to a plurality of upper electrodes of the capacitors in the peripheral circuit region to connect at least a portion of the capacitors in parallel. The first node is formed at substantially the same level as a bit line in a cell array region and is formed of the same material used to form the bit line.

Abstract translation: 提供了具有外围电路电容器的半导体存储器件。 在半导体存储器件中，第一节点电连接到外围电路区域中的多个电容器的多个下电极，以平行地连接至少一部分电容器。 第二节点电连接到外围电路区域中的电容器的多个上电极，以平行地连接至少一部分电容器。 第一节点形成在与单元阵列区域中的位线基本相同的电平上，并且由用于形成位线的相同材料形成。