公开(公告)号：US20140106569A1

公开(公告)日：2014-04-17

申请号：US13949600

申请日：2013-07-24

Applicant: Jung-Ik OH ,  Daehyun JANG ,  Ha-Na KIM ,  Seongsoo LEE

Inventor： Jung-Ik OH ,  Daehyun JANG ,  Ha-Na KIM ,  Seongsoo LEE

IPC: H01L21/308

CPC classification number: H01L21/308 ,  H01L21/31144 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: According to example embodiments of inventive concepts, a method of fabricating a 3D semiconductor device may include: forming a stack structure including a plurality of horizontal layers sequentially stacked on a substrate including a cell array region and a contact region; forming a first mask pattern covering the cell array region and defining openings extending in one direction over the contact region; performing a first etching process with a first etch-depth using the first mask pattern as an etch mask on the stack structure; forming a second mask pattern covering the cell array region and exposing a part of the contact region; and performing a second etching process with a second etch-depth using the second mask pattern as an etch mask structure on the stack structure. The second etch-depth may be greater than the first etch-depth.

Abstract translation: 根据发明构思的示例性实施例，制造3D半导体器件的方法可以包括：形成包括依次层叠在包括单元阵列区域和接触区域的基板上的多个水平层的堆叠结构; 形成覆盖所述单元阵列区域并限定在所述接触区域上沿一个方向延伸的开口的第一掩模图案; 使用所述第一掩模图案作为所述堆叠结构上的蚀刻掩模，利用第一蚀刻深度执行第一蚀刻工艺; 形成覆盖所述单元阵列区域并露出所述接触区域的一部分的第二掩模图案; 以及使用所述第二掩模图案作为所述堆叠结构上的蚀刻掩模结构，用第二蚀刻深度执行第二蚀刻工艺。 第二蚀刻深度可以大于第一蚀刻深度。

公开(公告)号：US20160133630A1

公开(公告)日：2016-05-12

申请号：US14792114

申请日：2015-07-06

Applicant: Ha-Na KIM ,  Dae-Hyun JANG ,  Jung-Ik OH

Inventor： Ha-Na KIM ,  Dae-Hyun JANG ,  Jung-Ik OH

IPC: H01L27/105 ,  H01L21/48 ,  H01L27/02

CPC classification number: H01L27/1052 ,  H01L21/481 ,  H01L21/4846 ,  H01L21/486 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A method of manufacturing a vertical memory device includes: providing a substrate including a cell array region and a peripheral circuit region; forming a mold structure in the cell array region; forming a mold protection film in a portion of the cell array region and the peripheral circuit region, the mold protection film contacting the mold structure; forming an opening for a common source line that passes through the mold structure and extends in a first direction perpendicular to a top surface of the substrate; forming a peripheral circuit contact hole that passes through the mold protection film and extends in the first direction in the peripheral circuit region; and simultaneously forming a first contact plug and a second contact plug, respectively, in the opening for the common source line and in the peripheral circuit contact hole.

Abstract translation: 制造垂直存储器件的方法包括：提供包括单元阵列区域和外围电路区域的衬底; 在电池阵列区域中形成模具结构; 在电池阵列区域和外围电路区域的一部分中形成保护膜，模具保护膜与模具结构接触; 形成用于通过所述模具结构并沿垂直于所述基板的顶表面的第一方向延伸的共同源极线的开口; 形成通过所述保护膜并沿所述外围电路区域沿所述第一方向延伸的外围电路接触孔; 同时在公共源极线的开口和外围电路接触孔中分别形成第一接触插塞和第二接触插塞。