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    METHOD OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND THREE-DIMENSIONAL SEMICONDUCTOR DEVICE FABRICATED USING THE SAME
    1.
    发明申请
    METHOD OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND THREE-DIMENSIONAL SEMICONDUCTOR DEVICE FABRICATED USING THE SAME 有权
    制造三维半导体器件的方法和使用其制造的三维半导体器件

    公开(公告)号：US20140106569A1

    公开(公告)日：2014-04-17

    申请号：US13949600

    申请日：2013-07-24

    申请人： Jung-Ik OH ,  Daehyun JANG ,  Ha-Na KIM ,  Seongsoo LEE

    发明人： Jung-Ik OH ,  Daehyun JANG ,  Ha-Na KIM ,  Seongsoo LEE

    IPC分类号： H01L21/308

    CPC分类号： H01L21/308 ,  H01L21/31144 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    摘要： According to example embodiments of inventive concepts, a method of fabricating a 3D semiconductor device may include: forming a stack structure including a plurality of horizontal layers sequentially stacked on a substrate including a cell array region and a contact region; forming a first mask pattern covering the cell array region and defining openings extending in one direction over the contact region; performing a first etching process with a first etch-depth using the first mask pattern as an etch mask on the stack structure; forming a second mask pattern covering the cell array region and exposing a part of the contact region; and performing a second etching process with a second etch-depth using the second mask pattern as an etch mask structure on the stack structure. The second etch-depth may be greater than the first etch-depth.

    摘要翻译： 根据发明构思的示例性实施例，制造3D半导体器件的方法可以包括：形成包括依次层叠在包括单元阵列区域和接触区域的基板上的多个水平层的堆叠结构; 形成覆盖所述单元阵列区域并限定在所述接触区域上沿一个方向延伸的开口的第一掩模图案; 使用所述第一掩模图案作为所述堆叠结构上的蚀刻掩模，利用第一蚀刻深度执行第一蚀刻工艺; 形成覆盖所述单元阵列区域并露出所述接触区域的一部分的第二掩模图案; 以及使用所述第二掩模图案作为所述堆叠结构上的蚀刻掩模结构，用第二蚀刻深度执行第二蚀刻工艺。 第二蚀刻深度可以大于第一蚀刻深度。

    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    2.
    发明申请
    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    垂直存储器件及其制造方法

    公开(公告)号：US20160133630A1

    公开(公告)日：2016-05-12

    申请号：US14792114

    申请日：2015-07-06

    申请人： Ha-Na KIM ,  Dae-Hyun JANG ,  Jung-Ik OH

    发明人： Ha-Na KIM ,  Dae-Hyun JANG ,  Jung-Ik OH

    IPC分类号： H01L27/105 ,  H01L21/48 ,  H01L27/02

    CPC分类号： H01L27/1052 ,  H01L21/481 ,  H01L21/4846 ,  H01L21/486 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    摘要： A method of manufacturing a vertical memory device includes: providing a substrate including a cell array region and a peripheral circuit region; forming a mold structure in the cell array region; forming a mold protection film in a portion of the cell array region and the peripheral circuit region, the mold protection film contacting the mold structure; forming an opening for a common source line that passes through the mold structure and extends in a first direction perpendicular to a top surface of the substrate; forming a peripheral circuit contact hole that passes through the mold protection film and extends in the first direction in the peripheral circuit region; and simultaneously forming a first contact plug and a second contact plug, respectively, in the opening for the common source line and in the peripheral circuit contact hole.

    摘要翻译： 制造垂直存储器件的方法包括：提供包括单元阵列区域和外围电路区域的衬底; 在电池阵列区域中形成模具结构; 在电池阵列区域和外围电路区域的一部分中形成保护膜，模具保护膜与模具结构接触; 形成用于通过所述模具结构并沿垂直于所述基板的顶表面的第一方向延伸的共同源极线的开口; 形成通过所述保护膜并沿所述外围电路区域沿所述第一方向延伸的外围电路接触孔; 同时在公共源极线的开口和外围电路接触孔中分别形成第一接触插塞和第二接触插塞。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICES HAVING VERTICAL CELLS
    6.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICES HAVING VERTICAL CELLS 审中-公开
    制造具有垂直细胞的半导体器件的方法

    公开(公告)号：US20150311153A1

    公开(公告)日：2015-10-29

    申请号：US14795352

    申请日：2015-07-09

    申请人： Jung-Ik OH ,  Dae-Hyun JANG ,  Kyoung-Sub SHIN

    发明人： Jung-Ik OH ,  Dae-Hyun JANG ,  Kyoung-Sub SHIN

    IPC分类号： H01L23/528 ,  H01L27/115

    CPC分类号： H01L27/11565 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    摘要： According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, dummy area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask.

    摘要翻译： 根据示例性实施例，制造半导体器件的方法包括：通过在单元，第一焊盘区域，虚拟区域和第二焊盘上交替堆叠多个层间绝缘和牺牲层来形成包括上部和下部初级堆叠结构的预备叠层结构 基材面积; 去除所述第二焊盘区域上的所述上部初级堆叠结构的整个部分; 形成在所述第一和第二焊盘区域的部分上限定开口的第一掩模; 通过由第一掩模曝光的预备叠层结构的剩余部分来蚀刻对应于多个层间绝缘层和牺牲层中的一个的蚀刻深度; 并且重复地进行第一阶梯形成处理，其包括收缩第一掩模的侧面并通过由缩小的第一掩模暴露的多个层间绝缘和牺牲层的剩余部分蚀刻蚀刻深度。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICES HAVING VERTICAL CELLS
    7.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICES HAVING VERTICAL CELLS 有权
    制造具有垂直细胞的半导体器件的方法

    公开(公告)号：US20140162420A1

    公开(公告)日：2014-06-12

    申请号：US14018578

    申请日：2013-09-05

    申请人： Jung-Ik OH ,  Dae-Hyun JANG ,  Kyoung-Sub SHIN

    发明人： Jung-Ik OH ,  Dae-Hyun JANG ,  Kyoung-Sub SHIN

    IPC分类号： H01L29/66

    CPC分类号： H01L27/11565 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    摘要： According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, sacrificial area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask.

    摘要翻译： 根据示例性实施例，制造半导体器件的方法包括：通过在电池，第一焊盘区域，牺牲区域和第二焊盘上交替堆叠多个层间绝缘和牺牲层来形成包括上部和下部预备堆叠结构的预备堆叠结构 基材面积; 去除所述第二焊盘区域上的所述上部初级堆叠结构的整个部分; 形成在所述第一和第二焊盘区域的部分上限定开口的第一掩模; 通过由第一掩模曝光的预备叠层结构的剩余部分来蚀刻对应于多个层间绝缘层和牺牲层中的一个的蚀刻深度; 并且重复地进行第一阶梯形成处理，其包括收缩第一掩模的侧面并通过由缩小的第一掩模暴露的多个层间绝缘和牺牲层的剩余部分蚀刻蚀刻深度。