公开(公告)号：US20080192543A1

公开(公告)日：2008-08-14

申请号：US11673771

申请日：2007-02-12

申请人： Jungwon Kim ,  Jiho Kim ,  Changduk Kim

发明人： Jungwon Kim ,  Jiho Kim ,  Changduk Kim

IPC分类号： G11C16/06

CPC分类号： G11C29/24 ,  G11C29/808 ,  G11C29/812

摘要： In a semiconductor memory which comprises a main memory array, redundant memory cells, and a plurality of repair fuse boxes, a method of selecting redundant memory cells in relation to repair fuse boxes, comprising testing redundant memory cells to determine whether they are valid or defective, and making a selection of redundant memory cells which allocates valid redundant memory cells to respective repair fuse boxes but which does not allocate defective redundant memory cells to any repair fuse boxes.

摘要翻译： 在包括主存储器阵列，冗余存储器单元和多个修复保险丝盒的半导体存储器中，选择与修复保险丝盒相关的冗余存储器单元的方法，包括测试冗余存储器单元以确定它们是有效还是有缺陷 并且选择冗余存储器单元，其将有效的冗余存储器单元分配给相应的修复保险丝盒，但不将有缺陷的冗余存储器单元分配给任何维修保险丝盒。

公开(公告)号：US08717059B2

公开(公告)日：2014-05-06

申请号：US13222744

申请日：2011-08-31

申请人： Changduk Kim

发明人： Changduk Kim

IPC分类号： G01R31/02

CPC分类号： H01L23/585 ,  G01R31/2884 ,  H01L22/34 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/859 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor die includes a substrate having a topside including active circuitry having an array of bond pads thereon separated by gaps including a minimum gap. At least a portion of the array of bond pads are connected to nodes in the active circuitry. At least one wire bond alignment sensing structure includes a first bond pad selected from the array of bond pads, and a guard element positioned along at least a portion of the first bond pad. The guard element is spaced apart by a distance shorter than the minimum gap from the first bond pad.

摘要翻译： 半导体管芯包括具有顶面的衬底，该顶面包括具有其上的接合焊盘阵列的有源电路，该间隙包括最小间隙。 接合焊盘阵列的至少一部分连接到有源电路中的节点。 至少一个引线键合对准检测结构包括从接合焊盘阵列中选择的第一接合焊盘，以及沿着第一接合焊盘的至少一部分定位的保护元件。 保护元件间隔开距离第一接合焊盘的最小间隙短的距离。

公开(公告)号：US07257038B2

公开(公告)日：2007-08-14

申请号：US11322252

申请日：2006-01-03

申请人： Michael A. Killian ,  Martin Versen ,  Grant McNeil ,  Zach Johnson ,  Changduk Kim

发明人： Michael A. Killian ,  Martin Versen ,  Grant McNeil ,  Zach Johnson ,  Changduk Kim

IPC分类号： G11C7/00

CPC分类号： G11C29/02 ,  G11C29/025 ,  G11C2029/1202 ,  G11C2029/5006

摘要： A semiconductor integrated circuit memory device, and test method for a memory device are provided in which an external wordline voltage is applied to a wordline of the memory device. A current on the wordline is measured as a result of application of the externally supplied wordline voltage. The measured current is compared to a reference value to determine whether the wordline has a defect, in particular a short-circuit defect. A tester device is connected to the memory device and supplies the external wordline voltage. The current measurement and comparison may be made internally by circuitry on the memory device or externally by circuitry in a tester device.

摘要翻译： 提供一种半导体集成电路存储器件以及用于存储器件的测试方法，其中外部字线电压被施加到存储器件的字线。 作为施加外部提供的字线电压的结果，测量字线上的电流。 将测量的电流与参考值进行比较以确定字线是否具有缺陷，特别是短路缺陷。 测试器设备连接到存储器件并提供外部字线电压。 当前的测量和比较可以由存储器件上的电路或外部由测试仪器中的电路在内部进行。

公开(公告)号：US20070153596A1

公开(公告)日：2007-07-05

申请号：US11322252

申请日：2006-01-03

申请人： Michael Kilian ,  Martin Versen ,  Grant McNeil ,  Zach Johnson ,  Changduk Kim

发明人： Michael Kilian ,  Martin Versen ,  Grant McNeil ,  Zach Johnson ,  Changduk Kim

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/02 ,  G11C29/025 ,  G11C2029/1202 ,  G11C2029/5006

摘要： A semiconductor integrated circuit memory device, and test method for a memory device are provided in which an external wordline voltage is applied to a wordline of the memory device. A current on the wordline is measured as a result of application of the externally supplied wordline voltage. The measured current is compared to a reference value to determine whether the wordline has a defect, in particular a short-circuit defect. A tester device is connected to the memory device and supplies the external wordline voltage. The current measurement and comparison may be made internally by circuitry on the memory device or externally by circuitry in a tester device.