公开(公告)号：US06621145B2

公开(公告)日：2003-09-16

申请号：US09866695

申请日：2001-05-30

申请人： Junichi Murota ,  Yosuke Shimamune ,  Masao Sakuraba ,  Takashi Matsuura

发明人： Junichi Murota ,  Yosuke Shimamune ,  Masao Sakuraba ,  Takashi Matsuura

IPC分类号： H01L29167

CPC分类号： H01L21/02576 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28525 ,  H01L21/28562 ,  H01L29/456

摘要： A metal-semiconductor junction comprises a wiring metal layer and a semiconductor layer. To reduce the contact resistance of the junction, a region doped with an n- or p-type impurity and having a high carrier concentration of 1021 cm−3 or more is provided in a near-surface part of the semiconductor layer (at a distance of 10 nm or less from the metal layer. The high-carrier concentration region is composed of n- or p-type impurity layers and IV-group semiconductor layers that have been alternately deposited upon another by means of, for example, vapor-phase growth.

摘要翻译： 金属 - 半导体结包括布线金属层和半导体层。 为了降低结的接触电阻，在半导体层的近表面部分设置掺杂有n型或p型杂质且具有1021cm-3以上的高载流子浓度的区域 与金属层相比为10nm以下，高载流子浓度区域由n型或p型杂质层和IV族半导体层构成，这些层通过例如气相 成长。

公开(公告)号：US06800544B2

公开(公告)日：2004-10-05

申请号：US10222777

申请日：2002-08-19

申请人： Junichi Murota ,  Yosuke Shimamune ,  Masao Sakuraba ,  Takashi Matsuura

发明人： Junichi Murota ,  Yosuke Shimamune ,  Masao Sakuraba ,  Takashi Matsuura

IPC分类号： H01L2128

CPC分类号： H01L21/02576 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28525 ,  H01L21/28562 ,  H01L29/456

摘要： A metal-semiconductor junction comprising a wiring metal layer and a semiconductor layer. To reduce the contact resistance of the junction, a region doped with an n- or p-type impurity and having a high carrier concentration of 1021 cm−3 or more is provided in a near-surface part of the semiconductor layer (at a distance of 10 nm or less from the metal layer. The high-carrier concentration region is composed of n- or p-type impurity layers and IV-group semiconductor layers that have been alternately deposited upon another by means of, for example, vapor-phase growth.

摘要翻译： 一种包括布线金属层和半导体层的金属 - 半导体结。 为了降低结的接触电阻，在半导体的近表面部分提供掺杂有n型或p型杂质并且具有10,23或更大载流子浓度的区域 层（距离金属层10nm以下的距离），高载流子浓度区域由n或p型杂质层和IV族半导体层构成，这些层被交替地沉积在另一层上， 例如，气相生长。

公开(公告)号：US08409958B2

公开(公告)日：2013-04-02

申请号：US13190696

申请日：2011-07-26

申请人： Katsuaki Ookoshi ,  Masatoshi Nishikawa ,  Yosuke Shimamune

发明人： Katsuaki Ookoshi ,  Masatoshi Nishikawa ,  Yosuke Shimamune

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device is provided. The method includes forming a gate electrode on a semiconductor substrate; forming a dopant implantation area in the semiconductor substrate by implanting a dopant in the semiconductor substrate, using the gate electrode as a mask; forming sidewalls on the gate electrode; forming a first recess by etching the semiconductor substrate, using the gate electrode and the sidewalls as a mask; forming a second recess by removing the dopant implantation area positioned below the sidewalls; and forming a source area and a drain area by causing a semiconductor material to grow in the first recess and the second recess.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在半导体衬底上形成栅电极; 通过使用栅电极作为掩模在半导体衬底中注入掺杂剂，在半导体衬底中形成掺杂剂注入区; 在所述栅电极上形成侧壁; 通过蚀刻所述半导体衬底，使用所述栅电极和所述侧壁作为掩模来形成第一凹部; 通过去除位于侧壁下方的掺杂剂注入区域形成第二凹槽; 以及通过使半导体材料在所述第一凹部和所述第二凹部中生长而形成源极区域和漏极区域。

公开(公告)号：US08278177B2

公开(公告)日：2012-10-02

申请号：US13240303

申请日：2011-09-22

申请人： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

发明人： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

摘要翻译： 在沟槽中通过外延生长法形成第一p型SiGe混晶层，形成第二p型SiGe混晶层。 在第二SiGe混晶层上形成第三p型SiGe混晶层。 从沟槽底部开始的第一SiGe混合晶体层的最上表面的高度低于沟槽的深度，硅衬底的表面是标准的。 从沟槽底部开始的第二SiGe混合晶体层的最上表面的高度高于沟槽的深度，硅衬底的表面是标准的。 第一和第三SiGe混晶层中的Ge浓度低于第二SiGe混晶层中的Ge浓度。

公开(公告)号：US07807524B2

公开(公告)日：2010-10-05

申请号：US12434944

申请日：2009-05-04

申请人： Young Suk Kim ,  Yosuke Shimamune

发明人： Young Suk Kim ,  Yosuke Shimamune

IPC分类号： H01L21/8238

摘要： A semiconductor device has: a semiconductor substrate made of a first semiconductor material; an n-channel field effect transistor formed in the semiconductor substrate and having n-type source/drain regions made of a second semiconductor material different from the first semiconductor material; and a p-channel field effect transistor formed in the semiconductor substrate and having p-type source/drain regions made of a third semiconductor material different from the first semiconductor material, wherein the second and third semiconductor materials are different materials. The semiconductor device having n- and p-channel transistors has improved performance by utilizing stress.

公开(公告)号：US20090215240A1

公开(公告)日：2009-08-27

申请号：US12434944

申请日：2009-05-04

申请人： Young Suk KIM ,  Yosuke Shimamune

发明人： Young Suk KIM ,  Yosuke Shimamune

IPC分类号： H01L21/336

CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device has: a semiconductor substrate made of a first semiconductor material; an n-channel field effect transistor formed in the semiconductor substrate and having n-type source/drain regions made of a second semiconductor material different from the first semiconductor material; and a p-channel field effect transistor formed in the semiconductor substrate and having p-type source/drain regions made of a third semiconductor material different from the first semiconductor material, wherein the second and third semiconductor materials are different materials. The semiconductor device having n- and p-channel transistors has improved performance by utilizing stress.

摘要翻译： 半导体器件具有：由第一半导体材料制成的半导体衬底; n型沟道场效应晶体管，其形成在所述半导体衬底中并且具有由与所述第一半导体材料不同的第二半导体材料制成的n型源/漏区; 以及形成在所述半导体衬底中并具有由与所述第一半导体材料不同的第三半导体材料制成的p型源极/漏极区的p沟道场效应晶体管，其中所述第二和第三半导体材料是不同的材料。 具有n沟道晶体管和p沟道晶体管的半导体器件通过利用应力来提高性能。

公开(公告)号：US20120329229A1

公开(公告)日：2012-12-27

申请号：US13603577

申请日：2012-09-05

申请人： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

发明人： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

公开(公告)号：US08338831B2

公开(公告)日：2012-12-25

申请号：US12826002

申请日：2010-06-29

申请人： Naoyoshi Tamura ,  Yosuke Shimamune ,  Hirotaka Maekawa

发明人： Naoyoshi Tamura ,  Yosuke Shimamune ,  Hirotaka Maekawa

IPC分类号： H01L21/8238 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： Recesses are formed in a pMOS region 2, and a SiGe layer is then formed so as to cover a bottom surface and a side surface of each of the recesses. Next, a SiGe layer containing Ge at a lower content than that in the SiGe layer is formed on each of the SiGe layers.

摘要翻译： 在pMOS区域2中形成凹部，然后形成SiGe层，以覆盖每个凹部的底表面和侧表面。 接下来，在每个SiGe层上形成含有比SiGe层低的含量的Ge的SiGe层。

公开(公告)号：US08158498B2

公开(公告)日：2012-04-17

申请号：US12379832

申请日：2009-03-03

申请人： Masashi Shima ,  Yosuke Shimamune ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

发明人： Masashi Shima ,  Yosuke Shimamune ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

IPC分类号： H01L21/44

CPC分类号： H01L29/165 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

摘要： A p-channel MOS transistor includes a gate electrode formed on a silicon substrate in correspondence to a channel region therein via a gate insulation film, the gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, and source and drain regions of p-type are formed in the substrate at respective outer sides of the sidewall insulation films, wherein each of the source and drain regions encloses a polycrystal region of p-type accumulating therein a compressive stress.

摘要翻译： P沟道MOS晶体管包括通过栅极绝缘膜对应于其沟道区域在硅衬底上形成的栅电极，在其各个侧壁表面上承载侧壁绝缘膜的栅极电极以及p型沟道MOS晶体管的源极和漏极区域 在侧壁绝缘膜的相应外侧的基板中形成，其中源极和漏极区域中的每一个围绕在其中积聚压缩应力的p型多晶体区域。

公开(公告)号：US07985641B2

公开(公告)日：2011-07-26

申请号：US12434944

申请日：2009-05-04

申请人： Young Suk Kim ,  Yosuke Shimamune

发明人： Young Suk Kim ,  Yosuke Shimamune

IPC分类号： H01L21/8238

CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device has: a semiconductor substrate made of a first semiconductor material; an n-channel field effect transistor formed in the semiconductor substrate and having n-type source/drain regions made of a second semiconductor material different from the first semiconductor material; and a p-channel field effect transistor formed in the semiconductor substrate and having p-type source/drain regions made of a third semiconductor material different from the first semiconductor material, wherein the second and third semiconductor materials are different materials. The semiconductor device having n- and p-channel transistors has improved performance by utilizing stress.

摘要翻译： 半导体器件具有：由第一半导体材料制成的半导体衬底; n型沟道场效应晶体管，其形成在所述半导体衬底中并且具有由与所述第一半导体材料不同的第二半导体材料制成的n型源/漏区; 以及形成在所述半导体衬底中并具有由与所述第一半导体材料不同的第三半导体材料制成的p型源极/漏极区的p沟道场效应晶体管，其中所述第二和第三半导体材料是不同的材料。 具有n沟道晶体管和p沟道晶体管的半导体器件通过利用应力来提高性能。