公开(公告)号：US20090138963A1

公开(公告)日：2009-05-28

申请号：US12292209

申请日：2008-11-13

申请人： Junichi Sato ,  Hitoshi Suzuki

发明人： Junichi Sato ,  Hitoshi Suzuki

IPC分类号： H04L9/32

CPC分类号： G06F12/1441

摘要： A CPU contained in an information processing apparatus in accordance an exemplary embodiment of the present invention outputs an access request including first access destination address information by a first program, and outputs a check request including second access destination address information when the execution program is switched from the first program to a second program as a result of a program call from the first program to the second program. A protection setting check portion contained in the information processing apparatus checks whether or not the check request including the second access destination address information conforms to protection setting for the first program based on memory protection information that is established in a memory protection information storage portion to detect a violation by a memory access request by the first program.

摘要翻译： 包含在根据本发明的示例性实施例的信息处理设备中的CPU通过第一程序输出包括第一访问目的地地址信息的访问请求，并且当执行程序被切换时输出包括第二访问目的地地址信息的检查请求 作为从第一程序到第二程序的程序调用的结果的第二程序的第一程序。 包含在信息处理设备中的保护设置检查部分基于在存储器保护信息存储部分中建立的存储器保护信息来检查包括第二接入目的地地址信息的检查请求是否符合第一程序的保护设置，以检测 由第一个程序的内存访问请求的违规。

公开(公告)号：US08381283B2

公开(公告)日：2013-02-19

申请号：US12292209

申请日：2008-11-13

申请人： Junichi Sato ,  Hitoshi Suzuki

发明人： Junichi Sato ,  Hitoshi Suzuki

IPC分类号： G06F12/14

CPC分类号： G06F12/1441

摘要： A CPU contained in an information processing apparatus in accordance an exemplary embodiment of the present invention outputs an access request including first access destination address information by a first program, and outputs a check request including second access destination address information when the execution program is switched from the first program to a second program as a result of a program call from the first program to the second program. A protection setting check portion contained in the information processing apparatus checks whether or not the check request including the second access destination address information conforms to protection setting for the first program based on memory protection information that is established in a memory protection information storage portion to detect a violation by a memory access request by the first program.

公开(公告)号：US08209565B2

公开(公告)日：2012-06-26

申请号：US12314493

申请日：2008-12-11

申请人： Yukihiko Akaike ,  Hitoshi Suzuki ,  Junichi Sato

发明人： Yukihiko Akaike ,  Hitoshi Suzuki ,  Junichi Sato

IPC分类号： G06F11/00

CPC分类号： G06F11/0772 ,  G06F11/0745 ,  G06F11/0793

摘要： A data processing device includes a computing circuit that accesses a peripheral device connected to through a internal bus, an internal bus connection circuit that is provided between the computing circuit and the internal bus, and switches an enable and a disable state of an access from the computing circuit to the internal bus, an exception notification controller that outputs an exception occurrence notification signal to the computing circuit based on an error occurred in the peripheral device, and a bus disablement controller that instructs the internal bus connection circuit to disable an access from the computing circuit to the internal bus in accordance with the notification of the exception occurrence notification signal, and instructs the internal bus connection circuit to cancel the disablement of the access in accordance with a start of an exception processing based on the exception occurrence notification signal.

摘要翻译： 数据处理装置包括：计算电路，其访问通过内部总线连接的外围设备;内部总线连接电路，其设置在所述计算电路和所述内部总线之间，并且从所述内部总线切换访问的使能和禁用状态 计算电路到内部总线，异常通知控制器，其基于外围设备中发生的错误向计算电路输出异常发生通知信号;以及总线禁用控制器，其指示内部总线连接电路禁止从 根据异常发生通知信号的通知计算电路到内部总线，并且根据异常发生通知信号的异常处理的开始，指示内部总线连接电路取消对该访问的禁止。

公开(公告)号：US20090172332A1

公开(公告)日：2009-07-02

申请号：US12314073

申请日：2008-12-03

申请人： Rika Ono ,  Hitoshi Suzuki ,  Junichi Sato

发明人： Rika Ono ,  Hitoshi Suzuki ,  Junichi Sato

IPC分类号： G06F12/14

CPC分类号： G06F12/1425

摘要： A instruction execution part of an information processing device outputs an access request including a first address information to specify an access destination based on an execution of an access command of an address space in a memory. The instruction execution part also outputs a check request including a second address information to specify a stack pointer point after extension based on an execution of a stack extension command to extend a stack included in the address space in the memory by updating a stack pointer. A protection violation detection section of the information processing device detects whether the access destination includes the plurality of the partial spaces by collating the first information with the memory protection information stored in the memory protection information storage section.

摘要翻译： 信息处理装置的指令执行部分基于存储器中的地址空间的访问命令的执行来输出包括第一地址信息的访问请求以指定访问目的地。 指令执行部分还输出包括第二地址信息的检查请求，以便在扩展之后基于堆栈扩展命令的执行来指定堆栈指针点，以通过更新堆栈指针来扩展包含在存储器中的地址空间中的栈。 信息处理设备的保护违规检测部分通过将第一信息与存储在存储器保护信息存储部分中的存储器保护信息进行对照来检测接入目的地是否包括多个部分空间。

公开(公告)号：US08234476B2

公开(公告)日：2012-07-31

申请号：US12314073

申请日：2008-12-03

申请人： Rika Ono ,  Hitoshi Suzuki ,  Junichi Sato

发明人： Rika Ono ,  Hitoshi Suzuki ,  Junichi Sato

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F15/00 ,  G06F9/30 ,  G06F9/40

CPC分类号： G06F12/1425

摘要： A instruction execution part of an information processing device outputs an access request including a first address information to specify an access destination based on an execution of an access command of an address space in a memory. The instruction execution part also outputs a check request including a second address information to specify a stack pointer point after extension based on an execution of a stack extension command to extend a stack included in the address space in the memory by updating a stack pointer. A protection violation detection section of the information processing device detects whether the access destination includes the plurality of the partial spaces by collating the first information with the memory protection information stored in the memory protection information storage section.

摘要翻译： 信息处理装置的指令执行部分基于存储器中的地址空间的访问命令的执行来输出包括第一地址信息的访问请求以指定访问目的地。 指令执行部分还输出包括第二地址信息的检查请求，以便在扩展之后基于堆栈扩展命令的执行来指定堆栈指针点，以通过更新堆栈指针来扩展包含在存储器中的地址空间中的栈。 信息处理设备的保护违规检测部分通过将第一信息与存储在存储器保护信息存储部分中的存储器保护信息进行对照来检测接入目的地是否包括多个部分空间。

公开(公告)号：US08209448B2

公开(公告)日：2012-06-26

申请号：US12292256

申请日：2008-11-14

申请人： Junichi Sato ,  Hitoshi Suzuki

发明人： Junichi Sato ,  Hitoshi Suzuki

IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F12/00

CPC分类号： G06F21/82 ,  G06F21/78 ,  G06F2221/2113

摘要： A data processing apparatus includes an arithmetic circuit and a peripheral device protection circuit that controls access of the arithmetic circuit to the peripheral devices. The peripheral device protection circuit has a first protection preset value and a second protection preset value set as a protection level higher than that of the first protection preset value. The peripheral device protection circuit includes: a setting selection circuit that generates access permission/denial information by referring to the first protection preset value and the second protection preset value when the arithmetic circuit operates at a first operation authority level, or by referring to the second protection preset value when the arithmetic circuit operates at the second operation authority level. An access protection circuit that determines permission/denial of access to the peripheral devices based on access information output from the arithmetic circuit and the access permission/denial information.

摘要翻译： 数据处理装置包括运算电路和外围设备保护电路，其控制运算电路对周边设备的访问。 外围设备保护电路具有设置为高于第一保护预设值的保护级别的第一保护预设值和第二保护预置值。 外围设备保护电路包括：设置选择电路，当运算电路以第一操作授权级别运行时，通过参考第一保护预置值和第二保护预设值产生访问允许/拒绝信息，或者参考第二 运算电路在第二操作权限级别运行时的保护预置值。 访问保护电路，根据从算术电路输出的访问信息和访问许可/拒绝信息，确定对外围设备的访问权限/拒绝。

公开(公告)号：US20090172231A1

公开(公告)日：2009-07-02

申请号：US12314493

申请日：2008-12-11

申请人： Yukihiko Akaike ,  Hitoshi Suzuki ,  Junichi Sato

发明人： Yukihiko Akaike ,  Hitoshi Suzuki ,  Junichi Sato

IPC分类号： G06F13/24

CPC分类号： G06F11/0772 ,  G06F11/0745 ,  G06F11/0793

摘要： A data processing device includes a computing circuit that accesses a peripheral device connected to through a internal bus, an internal bus connection circuit that is provided between the computing circuit and the internal bus, and switches an enable and a disable state of an access from the computing circuit to the internal bus, an exception notification controller that outputs an exception occurrence notification signal to the computing circuit based on an error occurred in the peripheral device, and a bus disablement controller that instructs the internal bus connection circuit to disable an access from the computing circuit to the internal bus in accordance with the notification of the exception occurrence notification signal, and instructs the internal bus connection circuit to cancel the disablement of the access in accordance with a start of an exception processing based on the exception occurrence notification signal.

摘要翻译： 数据处理装置包括：计算电路，其访问通过内部总线连接的外围设备;内部总线连接电路，其设置在所述计算电路和所述内部总线之间，并且从所述内部总线切换访问的使能和禁用状态 计算电路到内部总线，异常通知控制器，其基于外围设备中发生的错误向计算电路输出异常发生通知信号;以及总线禁用控制器，其指示内部总线连接电路禁止从 根据异常发生通知信号的通知计算电路到内部总线，并且根据异常发生通知信号的异常处理的开始，指示内部总线连接电路取消对该访问的禁止。

公开(公告)号：US20090144465A1

公开(公告)日：2009-06-04

申请号：US12292256

申请日：2008-11-14

申请人： Junichi Sato ,  Hitoshi Suzuki

发明人： Junichi Sato ,  Hitoshi Suzuki

IPC分类号： G06F21/04

CPC分类号： G06F21/82 ,  G06F21/78 ,  G06F2221/2113

摘要： A data processing apparatus includes an arithmetic circuit and a peripheral device protection circuit that controls access of the arithmetic circuit to the peripheral devices. The peripheral device protection circuit has a first protection preset value and a second protection preset value set as a protection level higher than that of the first protection preset value. The peripheral device protection circuit includes: a setting selection circuit that generates access permission/denial information by referring to the first protection preset value and the second protection preset value when the arithmetic circuit operates at a first operation authority level, or by referring to the second protection preset value when the arithmetic circuit operates at the second operation authority level. An access protection circuit that determines permission/denial of access to the peripheral devices based on access information output from the arithmetic circuit and the access permission/denial information.

摘要翻译： 数据处理装置包括运算电路和外围设备保护电路，其控制运算电路对周边设备的访问。 外围设备保护电路具有设置为高于第一保护预设值的保护级别的第一保护预设值和第二保护预置值。 外围设备保护电路包括：设置选择电路，当运算电路以第一操作授权级别运行时，通过参考第一保护预置值和第二保护预设值产生访问允许/拒绝信息，或者参考第二 运算电路在第二操作权限级别运行时的保护预置值。 访问保护电路，根据从算术电路输出的访问信息和访问许可/拒绝信息，确定对外围设备的访问权限/拒绝。

公开(公告)号：US08717855B2

公开(公告)日：2014-05-06

申请号：US13597927

申请日：2012-08-29

申请人： Junichi Sato ,  Shunya Shiraishi

发明人： Junichi Sato ,  Shunya Shiraishi

IPC分类号： G04B19/06

CPC分类号： G04B19/065 ,  G04B19/087

摘要： A dial plate structure includes first and second dial plates and a rotary indicator. The first dial plate has a first opening or a first cutout. The second dial plate is arranged under the first dial plate and has a plurality of function display portions exposed through the opening or the cutout. The rotary indicator is arranged between the first and second dial plates and has a function indicator to selectively indicate one of the function display portions by rotation. The rotary indicator is partially exposed through the opening or the cutout. The rotary indicator has, on the surface thereof, a plurality of index markers respectively corresponding to the function display portions. The first dial plate has a second opening or a second cutout to expose one of the index markers when the function indicator indicates one of the function display portions corresponding to the indicated function display portion.

摘要翻译： 表盘结构包括第一和第二拨盘和旋转指示器。 第一刻度盘具有第一开口或第一切口。 第二表盘布置在第一拨盘下方，并且具有通过开口或切口暴露的多个功能显示部。 旋转指示器布置在第一和第二表盘之间，并且具有功能指示器，以通过旋转来选择性地指示功能显示部分之一。 旋转指示器通过开口或切口部分露出。 旋转指示器在其表面上分别对应于功能显示部分的多个索引标记。 当功能指示符指示与所指示的功能显示部分相对应的功能显示部分之一时，第一刻度盘具有第二开口或第二切口以暴露索引标记之一。

公开(公告)号：US08569003B2

公开(公告)日：2013-10-29

申请号：US13908686

申请日：2013-06-03

申请人： Satoshi Inouye ,  Yuiko Sahara ,  Junichi Sato

发明人： Satoshi Inouye ,  Yuiko Sahara ,  Junichi Sato

IPC分类号： C12Q1/66

CPC分类号： G01N33/581 ,  C07K14/43509 ,  C07K2319/00 ,  C07K2319/20 ,  C07K2319/60 ,  C12N9/0069 ,  C12Q1/66

摘要： The fusion protein comprising (1) a first region comprising the amino acid sequence of SEQ ID NO: 18 and (2) a second region comprising an amino acid sequence for a polypeptide containing at least one cysteine residue for binding to other useful compound via the thiol group can be modified by chemical modification, and thus has a high catalytic ability for a luminescence activity and is highly available for general purposes.