公开(公告)号：US07532560B2

公开(公告)日：2009-05-12

申请号：US10906541

申请日：2005-02-24

申请人： Jyh-Fong Lin ,  Yi-Bin Hsieh ,  Chih-Chang Chien

发明人： Jyh-Fong Lin ,  Yi-Bin Hsieh ,  Chih-Chang Chien

IPC分类号： G11B7/00 ,  G11B5/09

CPC分类号： G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10314

摘要： A signal processing circuit for adjusting an input signal and generating a corresponding digital output signal in an optical disk driver is provided. The signal processing circuit includes an attenuator for receiving and attenuating the input signal and then generating an attenuated output signal; a gain controllable amplifier for receiving and amplifying the input signal and then generating an amplified output signal; a control unit providing a control signal and a select signal, the control signal is directed to the attenuator and the gain controllable amplifier for enabling/disabling the attenuator and the gain controllable amplifier and for controlling their gains such that one of the attenuator and gain controllable amplifier is enabled at a time; and a waveform adjuster circuit for adjusting the amplified/attenuated output signal delivered from the gain controllable amplifier or the attenuator so as to generate the digital signal related to the input signal.

摘要翻译： 提供了一种用于在光盘驱动器中调整输入信号并产生相应的数字输出信号的信号处理电路。 信号处理电路包括：衰减器，用于接收和衰减输入信号，然后产生衰减的输出信号; 增益可控放大器，用于接收和放大输入信号，然后产生放大的输出信号; 提供控制信号和选择信号的控制单元，控制信号被引导到衰减器和增益可控放大器，用于使能/禁用衰减器和增益可控放大器并用于控制其增益，使得衰减器和增益中的一个可控 放大器一次启用; 以及用于调整从增益可控放大器或衰减器传送的放大/衰减的输出信号的波形调节器电路，以便产生与输入信号有关的数字信号。

公开(公告)号：US20050157626A1

公开(公告)日：2005-07-21

申请号：US10906541

申请日：2005-02-24

申请人： Jyh-Fong Lin ,  Yi-Bin Hsieh ,  Chih-Chang Chien

发明人： Jyh-Fong Lin ,  Yi-Bin Hsieh ,  Chih-Chang Chien

IPC分类号： G11B3/00 ,  G11B5/09 ,  G11B20/10

CPC分类号： G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10314

摘要： A signal processing circuit for adjusting an input signal and generating a corresponding digital output signal in an optical disk driver is provided. The signal processing circuit includes an attenuator for receiving and attenuating the input signal and then generating an attenuated output signal; a gain controllable amplifier for receiving and amplifying the input signal and then generating an amplified output signal; a control unit providing a control signal and a select signal, the control signal is directed to the attenuator and the gain controllable amplifier for enabling/disabling the attenuator and the gain controllable amplifier and for controlling their gains such that one of the attenuator and gain controllable amplifier is enabled at a time; and a waveform adjuster circuit for adjusting the amplified/attenuated output signal delivered from the gain controllable amplifier or the attenuator so as to generate the digital signal related to the input signal.

摘要翻译： 提供了一种用于在光盘驱动器中调整输入信号并产生相应的数字输出信号的信号处理电路。 信号处理电路包括：衰减器，用于接收和衰减输入信号，然后产生衰减的输出信号; 增益可控放大器，用于接收和放大输入信号，然后产生放大的输出信号; 提供控制信号和选择信号的控制单元，控制信号被引导到衰减器和增益可控放大器，用于使能/禁用衰减器和增益可控放大器并用于控制其增益，使得衰减器和增益中的一个可控 放大器一次启用; 以及用于调整从增益可控放大器或衰减器传送的放大/衰减的输出信号的波形调节器电路，以产生与输入信号有关的数字信号。

公开(公告)号：US07016450B2

公开(公告)日：2006-03-21

申请号：US10064215

申请日：2002-06-21

申请人： Jyh-Fong Lin ,  Hsin-Chieh Lin ,  Yi-Bin Hsieh

发明人： Jyh-Fong Lin ,  Hsin-Chieh Lin ,  Yi-Bin Hsieh

IPC分类号： H03D3/24

CPC分类号： H03L7/0891 ,  H03L7/093 ,  H03L7/18

摘要： A clock recovery circuit for generating an output signal that is synchronized with an input signal. The clock recovery circuit includes a charge pump, a first filter, an oscillator, a switch circuit, and a second filter. When the charge pump operates, the switch circuit will disconnect the first filter from the oscillator. Additionally, when the charge pump stops operating, the switch circuit will connect the first filter and the oscillator such that the oscillator adjusts a frequency or phase of the output signal according to the output voltage of the first filter.

摘要翻译： 一种用于产生与输入信号同步的输出信号的时钟恢复电路。 时钟恢复电路包括电荷泵，第一滤波器，振荡器，开关电路和第二滤波器。 当电荷泵运行时，开关电路将使第一个滤波器与振荡器断开。 此外，当电荷泵停止工作时，开关电路将连接第一滤波器和振荡器，使得振荡器根据第一滤波器的输出电压来调节输出信号的频率或相位。

公开(公告)号：US07333039B2

公开(公告)日：2008-02-19

申请号：US11537678

申请日：2006-10-02

申请人： Wu-Hung Lu ,  Yi-Bin Hsieh

发明人： Wu-Hung Lu ,  Yi-Bin Hsieh

IPC分类号： H03M1/00

CPC分类号： H03M1/0604 ,  H03M1/0682 ,  H03M1/403

摘要： A cyclic pipeline analog to digital converter includes a dual mode sample and hold circuit, a multiplying digital to analog converter (MDAC), a sub-analog to digital converter (sub-ADC) and a decoder. The dual mode sample and hold circuit has a charge-redistribution mode and a flip-around mode. The dual mode sample and hold circuit receives first and second input voltages and first and second feedback voltages and generates a differential output signal pair. The MDAC receives the differential output signal pair and a digital multiplying word and generates the first and second feedback voltages. The sub-ADC receives the differential output signal pair and generates the digital multiplying word and a digital output word. The decoder converts the digital output word to a digital output corresponding to the first and second input voltages.

摘要翻译： 循环管线模数转换器包括双模式采样和保持电路，乘法数模转换器（MDAC），子模数转换器（sub-ADC）和解码器。 双模式采样和保持电路具有电荷再分配模式和翻转模式。 双模式采样和保持电路接收第一和第二输入电压以及第一和第二反馈电压并产生差分输出信号对。 MDAC接收差分输出信号对和数字乘法字，并产生第一和第二反馈电压。 子ADC接收差分输出信号对并产生数字乘法字和数字输出字。 解码器将数字输出字转换成对应于第一和第二输入电压的数字输出。

公开(公告)号：US07113029B2

公开(公告)日：2006-09-26

申请号：US11103874

申请日：2005-04-12

申请人： Yi-Bin Hsieh ,  Wen-Hui Chen

发明人： Yi-Bin Hsieh ,  Wen-Hui Chen

IPC分类号： H03K5/00

CPC分类号： H03H11/1291

摘要： Transconductance filter circuits. A transconductor includes two inputs for receiving two differential voltages, and a first output terminal and a second output terminal for outputting two differential signals. A first capacitor array includes at least one first switch capacitor unit controlled by a first signal, and a first equivalent capacitor coupled between the first output terminal and the second output terminal when the first signal is enabled. two second capacitor arrays each includes at least one second switch capacitor unit controlled by a second signal, two second equivalent capacitors respectively coupled between the first output terminal and a ground level, and between the second output terminal and the ground level when the second signal is enabled. The capacitance of the first equivalent capacitor exceeds that of the two second equivalent capacitors connected in serial.

公开(公告)号：US06927642B2

公开(公告)日：2005-08-09

申请号：US10810016

申请日：2004-03-26

申请人： Yi-Bin Hsieh

发明人： Yi-Bin Hsieh

IPC分类号： H03K5/156 ,  H03L7/089 ,  H03L7/099 ,  H03L7/18 ,  H03L1/00

CPC分类号： H03L7/099 ,  H03K5/1565 ,  H03L7/0891 ,  H03L7/18

摘要： A duty cycle correction method converts a pair of differential analog signals from an oscillator into an output pulse signal with 50% of duty cycle. The pulse signal has the same frequency as that of each of the differential analog signals. The duty cycle correction method processes the pair of differential analog signals into a first digital pulse signal and a second digital pulse signal, wherein the first digital pulse signal and the second digital pulse signal have a specified phase difference therebetween, frequency-divides the first digital pulse signal and the second digital pulse signal into a third digital pulse signal and a fourth digital pulse signal, and generates the output pulse signal according to the third and fourth digital pulse signals. The output pulse signal can be generated by performing an exclusive OR operation of the third and fourth digital pulse signals.

摘要翻译： 占空比校正方法将来自振荡器的一对差分模拟信号转换成占空比为50％的输出脉冲信号。 脉冲信号的频率与差分模拟信号的频率相同。 占空比校正方法将该对差分模拟信号处理成第一数字脉冲信号和第二数字脉冲信号，其中第一数字脉冲信号和第二数字脉冲信号之间具有规定的相位差，将第一数字脉冲信号和第二数字脉冲信号分频， 脉冲信号和第二数字脉冲信号转换成第三数字脉冲信号和第四数字脉冲信号，并根据第三和第四数字脉冲信号产生输出脉冲信号。 可以通过执行第三和第四数字脉冲信号的异或运算来产生输出脉冲信号。

公开(公告)号：US20080143306A1

公开(公告)日：2008-06-19

申请号：US11802880

申请日：2007-05-25

申请人： Hisn-Kuang Chen ,  Yi-Bin Hsieh ,  Che-Wei Hsu

发明人： Hisn-Kuang Chen ,  Yi-Bin Hsieh ,  Che-Wei Hsu

IPC分类号： H03F3/45 ,  G05F1/10

CPC分类号： H03G1/0023 ,  H03G1/0029

摘要： A voltage control circuit is provided. The voltage control circuit comprises a control voltage source, a current generating unit, and an output voltage generating unit. The control voltage source inputs a single end control voltage. The current generating unit coupled to the control voltage source and a ground generates a first current according to the single end control voltage. The output voltage generating unit coupled to the current generating unit, receives a reference voltage, and generates a first output voltage and a second output voltage according to the first current and the reference voltage. A value of the first output voltage is greater than a value of the second output voltage.

摘要翻译： 提供电压控制电路。 电压控制电路包括控制电压源，电流产生单元和输出电压产生单元。 控制电压源输入单端控制电压。 耦合到控制电压源和接地的电流产生单元根据单端控制电压产生第一电流。 耦合到电流产生单元的输出电压产生单元接收参考电压，并根据第一电流和参考电压产生第一输出电压和第二输出电压。 第一输出电压的值大于第二输出电压的值。

公开(公告)号：US20080068087A1

公开(公告)日：2008-03-20

申请号：US11567199

申请日：2006-12-05

申请人： Yi-Bin Hsieh ,  Hisn-Kuang Chen ,  Che-Wei Hsu

发明人： Yi-Bin Hsieh ,  Hisn-Kuang Chen ,  Che-Wei Hsu

IPC分类号： H03G3/10

CPC分类号： H03G3/30 ,  H03K5/023

摘要： An automatic-gain control circuit includes a variable-gain amplifier, a peak-detecting circuit, and an adjustable charge/discharge circuit. The variable-gain amplifier receives an input signal and adjusts the input signal based on a gain-factor control signal for generating a corresponding output signal. The peak-detecting circuit is coupled to the variable-gain amplifier for generating a comparing signal according to a reference signal and the output signal. The adjustable charge/discharge circuit is coupled to the peak-detecting circuit and the variable-gain amplifier for outputting a charge current or a discharge current based on the comparing signal, thereby generating the gain-factor control signal. The ratio between the charge current and the discharge current is adjustable.

摘要翻译： 自动增益控制电路包括可变增益放大器，峰值检测电路和可调节充电/放电电路。 可变增益放大器接收输入信号，并且基于用于产生对应的输出信号的增益因子控制信号调整输入信号。 峰值检测电路耦合到可变增益放大器，用于根据参考信号和输出信号产生比较信号。 可调节充电/放电电路耦合到峰值检测电路和可变增益放大器，用于基于比较信号输出充电电流或放电电流，从而产生增益因子控制信号。 充电电流和放电电流之间的比例是可调的。

公开(公告)号：US06737927B2

公开(公告)日：2004-05-18

申请号：US10270893

申请日：2002-10-15

申请人： Yi-Bin Hsieh

发明人： Yi-Bin Hsieh

IPC分类号： H03B100

CPC分类号： H03L7/099 ,  H03K5/1565 ,  H03L7/0891 ,  H03L7/18

摘要： A duty cycle correction circuit is provided for converting a pair of differential analog signals from an oscillator into an output pulse signal with 50% of duty cycle. The pulse signal has the same frequency as that of each of the differential analog signals. The duty cycle correction circuit includes a first differential-to-single-ended buffer circuit, a second differential-to-single-ended buffer circuit, a first frequency divider, a second frequency divider and a symmetrical exclusive OR element. The first and the second differential-to-single-ended buffer circuits are used for processing the pair of differential analog signals into a first and a second digital pulse signals, respectively. The first and the second frequency dividers are employed for frequency-dividing the first and the digital pulse signal into a third and a fourth digital pulse signal, respectively. The symmetrical exclusive OR element is used for performing an exclusive OR operation so as to produce the output pulse signal.

摘要翻译： 提供了一种占空比校正电路，用于将来自振荡器的一对差分模拟信号转换成占空比为50％的输出脉冲信号。 脉冲信号的频率与差分模拟信号的频率相同。 占空比校正电路包括第一差分到单端缓冲电路，第二差分到单端缓冲电路，第一分频器，第二分频器和对称异或元件。 第一和第二差分到单端缓冲电路分别用于将一对差分模拟信号处理成第一和第二数字脉冲信号。 第一和第二分频器分别用于将第一和第二数字脉冲信号分频成第三和第四数字脉冲信号。 对称异或元件用于执行异或运算，以产生输出脉冲信号。

公开(公告)号：US08531216B1

公开(公告)日：2013-09-10

申请号：US13557172

申请日：2012-07-24

申请人： Jin-Xiao Wu ,  Heng-Chih Lin ,  Yi-Bin Hsieh

发明人： Jin-Xiao Wu ,  Heng-Chih Lin ,  Yi-Bin Hsieh

IPC分类号： H03L7/00

CPC分类号： H03J7/04

摘要： The present invention discloses an electronic apparatus. The electronic apparatus comprises a reference oscillator, for generating a reference clock; a first communications module, comprising a first auto frequency control unit, for detecting a first frequency offset between the first communications module and a first communication device and generating a first detecting result; and a first frequency synthesizer, for adjusting the reference clock according to the first detecting result, to generate a first baseband clock; and a second communications module, comprising a second auto frequency control unit, for detecting a second frequency offset between the second communications module and a second communication device and generating a second detecting result; a second frequency synthesizer, for receiving and outputting the first baseband clock; and a compensation unit, for adjusting the first baseband clock according to the first detecting result and the second detecting result, to generate a second baseband clock.

摘要翻译： 本发明公开了一种电子设备。 电子设备包括用于产生参考时钟的参考振荡器; 第一通信模块，包括第一自动频率控制单元，用于检测第一通信模块和第一通信设备之间的第一频率偏移并产生第一检测结果; 以及第一频率合成器，用于根据第一检测结果调整参考时钟，以产生第一基带时钟; 以及第二通信模块，包括第二自动频率控制单元，用于检测所述第二通信模块和第二通信设备之间的第二频率偏移并产生第二检测结果; 第二频率合成器，用于接收和输出第一基带时钟; 以及补偿单元，用于根据第一检测结果和第二检测结果调整第一基带时钟，以产生第二基带时钟。