公开(公告)号：US20170053869A1

公开(公告)日：2017-02-23

申请号：US14985969

申请日：2015-12-31

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Atsuko SAKATA ,  Takeshi ISHIZAKI ,  Shinya OKUDA ,  Kei WATANABE ,  Masayuki KITAMURA ,  Satoshi WAKATSUKI ,  Daisuke IKENO ,  Junichi WADA ,  Hirotaka OGIHARA

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/3065 ,  H01L27/115 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/3065 ,  H01L21/76843 ,  H01L21/76864 ,  H01L27/11582 ,  H01L29/7881

Abstract: According to one embodiment, the stacked body includes a plurality of metal films, a plurality of silicon oxide films, and a plurality of intermediate films. The intermediate films are provided between the metal films and the silicon oxide films. The intermediate films contain silicon nitride. Nitrogen composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the metal films than on sides of interfaces between the intermediate films and the silicon oxide films. Silicon composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the silicon oxide films than on sides of interfaces between the intermediate films and the metal films.

Abstract translation: 根据一个实施例，层叠体包括多个金属膜，多个氧化硅膜和多个中间膜。 中间膜设置在金属膜和氧化硅膜之间。 中间膜含有氮化硅。 在中间膜和金属膜之间的界面侧，中间膜的氮组成比在中间膜和氧化硅膜之间的界面侧更高。 在中间膜和氧化硅膜之间的界面侧，中间膜的硅组成比在中间膜和金属膜之间的界面侧更高。

公开(公告)号：US20130270506A1

公开(公告)日：2013-10-17

申请号：US13788596

申请日：2013-03-07

Applicant: Kabushiki Kaisha Toshiba

Inventor： Ichiro MIZUSHIMA ,  Hirotaka OGIHARA ,  Kensuke TAKAHASHI ,  Masanobu BABA

IPC: H01L45/00

CPC classification number: H01L45/14 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/148 ,  H01L45/1616 ,  H01L45/1675

Abstract: A non-volatile semiconductor memory includes a word line extending in a first direction, a first electrode connected to the word line electrically, an ion diffusion layer with connected to the first electrode electrically, a second electrode connected to the ion diffusion layer electrically and formed of a metal to be diffused into the ion diffusion layer when a positive voltage is supplied thereto, and a bit line extending in a second direction perpendicular to the first direction, the bit line connected to the second electrode electrically. The ion diffusion layer has a first region disposed on the first electrode and a second region disposed between the first region and the second electrode, and the metal is more difficult to diffuse into the second region than into the first region.

Abstract translation: 非易失性半导体存储器包括：沿第一方向延伸的字线，电连接到字线的第一电极，电连接到第一电极的离子扩散层，电连接到离子扩散层的第二电极 当向其提供正电压时扩散到离子扩散层中的金属以及沿垂直于第一方向的第二方向延伸的位线，该位线与第二电极电连接。 离子扩散层具有设置在第一电极上的第一区域和设置在第一区域和第二电极之间的第二区域，并且金属比第一区域更难扩散到第二区域。

公开(公告)号：US20160300845A1

公开(公告)日：2016-10-13

申请号：US14828830

申请日：2015-08-18

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Takeshi ISHIZAKI ,  Junichi WADA ,  Atsuko SAKATA ,  Kei WATANABE ,  Masayuki KITAMURA ,  Daisuke IKENO ,  Satoshi WAKATSUKl ,  Hirotaka OGIHARA ,  Shinya OKUDA

IPC: H01L27/115 ,  H01L27/02 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a film having semi-conductivity or conductivity, and a memory film. The stacked body includes a plurality of metal layers, a plurality of insulating layers, and a plurality of intermediate layers stacked on a major surface of the substrate. The film extends in the stacked body in a stacking direction of the stacked body. The memory film is provided between the film and the metal layers. The metal layers are tungsten layers and the intermediate layers are tungsten nitride layers. Or the metal layers are molybdenum layers and the intermediate layers are molybdenum nitride layers.

Abstract translation: 根据一个实施例，半导体器件包括衬底，层叠体，具有半导电性或导电性的膜和存储膜。 堆叠体包括多个金属层，多个绝缘层和堆叠在基板的主表面上的多个中间层。 薄膜沿层叠体的层叠方向在层叠体上延伸。 记忆膜设置在膜和金属层之间。 金属层是钨层，中间层是氮化钨层。 或者金属层是钼层，中间层是氮化钼层。