公开(公告)号：US20170053869A1

公开(公告)日：2017-02-23

申请号：US14985969

申请日：2015-12-31

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Atsuko SAKATA ,  Takeshi ISHIZAKI ,  Shinya OKUDA ,  Kei WATANABE ,  Masayuki KITAMURA ,  Satoshi WAKATSUKI ,  Daisuke IKENO ,  Junichi WADA ,  Hirotaka OGIHARA

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/3065 ,  H01L27/115 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/3065 ,  H01L21/76843 ,  H01L21/76864 ,  H01L27/11582 ,  H01L29/7881

Abstract: According to one embodiment, the stacked body includes a plurality of metal films, a plurality of silicon oxide films, and a plurality of intermediate films. The intermediate films are provided between the metal films and the silicon oxide films. The intermediate films contain silicon nitride. Nitrogen composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the metal films than on sides of interfaces between the intermediate films and the silicon oxide films. Silicon composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the silicon oxide films than on sides of interfaces between the intermediate films and the metal films.

Abstract translation: 根据一个实施例，层叠体包括多个金属膜，多个氧化硅膜和多个中间膜。 中间膜设置在金属膜和氧化硅膜之间。 中间膜含有氮化硅。 在中间膜和金属膜之间的界面侧，中间膜的氮组成比在中间膜和氧化硅膜之间的界面侧更高。 在中间膜和氧化硅膜之间的界面侧，中间膜的硅组成比在中间膜和金属膜之间的界面侧更高。

公开(公告)号：US20160276204A1

公开(公告)日：2016-09-22

申请号：US14751603

申请日：2015-06-26

Applicant: Kabushiki Kaisha Toshiba

Inventor： Atsuko SAKATA ,  Kei Watanabe ,  Junichi Wada ,  Masayuki Kitamura ,  Takeshi Ishizaki ,  Shinya Okuda ,  Hirotaka Ogihara ,  Satoshi Wakatsuki ,  Daisuke Ikeno

IPC: H01L21/687 ,  C23C16/458 ,  H01J37/34 ,  H01L21/02

CPC classification number: H01L21/68764 ,  C23C14/568 ,  C23C16/4409 ,  C23C16/4585 ,  C23C16/54 ,  H01J37/32733 ,  H01J37/32899 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/67161 ,  H01L21/6719 ,  H01L21/67745 ,  H01L21/67757 ,  H01L21/68742 ,  H01L21/68771

Abstract: A method of manufacturing a semiconductor device uses a semiconductor manufacturing apparatus including a turn table allowing placement of at least first and second semiconductor substrates and being capable of moving positions of the first and the second semiconductor substrates by turning, a first film forming chamber, and a second film forming chamber. The first and the second film forming chambers are provided with an opening capable of loading and unloading the first and the second semiconductor substrates by lifting and lowering the first and the second semiconductor substrates placed on the turn table. The method includes transferring the first and the second semiconductor substrates between the first and the second film forming chambers by turning the turn fable and lifting and lowering the first and the second semiconductor substrates placed on the turn table; and forming a stack of films above the first and the second semiconductor substrates.

Abstract translation: 一种制造半导体器件的方法使用包括转台的半导体制造装置，其允许至少布置第一和第二半导体衬底，并且能够通过转动来移动第一和第二半导体衬底的位置，第一成膜室和 第二成膜室。 第一和第二成膜室设置有能够通过升高和降低放置在转台上的第一和第二半导体衬底来装载和卸载第一和第二半导体衬底的开口。 该方法包括：转动第一和第二成膜室之间转动第一和第二半导体衬底，并转动第一和第二半导体衬底，使第一和第二半导体衬底转动，并使放置在转台上的第一和第二半导体衬底升高和降低; 以及在第一和第二半导体衬底之上形成一叠薄膜。

公开(公告)号：US20180277667A1

公开(公告)日：2018-09-27

申请号：US15690251

申请日：2017-08-29

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hideki SEKIGUCHI ,  Keiko KAWAMURA ,  Kaori FUSE ,  Akira KOMATSU ,  Ryohei KITAO ,  Satoshi WAKATSUKI ,  Atsuko SAKATA ,  Koichi KUBO

IPC: H01L29/739 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L29/7397 ,  H01L21/043 ,  H01L29/417 ,  H01L29/456 ,  H01L29/7396

Abstract: A semiconductor device includes first and second electrodes, first semiconductor region of first conductivity type between the first and second electrodes, a second semiconductor region of second conductivity type between the first semiconductor region and the first electrode, a third semiconductor region of the second conductivity type between the first semiconductor region and the second electrode, a fourth semiconductor region of the first conductivity type between the third semiconductor region and the second electrode, a plurality of third electrodes between the second electrode and the first semiconductor region, wherein a gate insulating film is between each third electrode and the third semiconductor region, a fourth electrode extending between the third semiconductor region and the second electrode and electrically connected to the third semiconductor region and the second electrode, and a first insulating film between the second and electrodes. The fourth electrode is in ohmic contact with the third semiconductor region.

公开(公告)号：US20170263621A1

公开(公告)日：2017-09-14

申请号：US15258275

申请日：2016-09-07

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi WAKATSUKI ,  Atsuko SAKATA ,  Daisuke IKENO

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: According to one embodiment, a stacked body includes a plurality of metal layers stacked with an insulator interposed. A semiconductor body extends in a stacking direction through the stacked body. A charge storage portion is provided between the semiconductor body and one of the metal layers. A metal nitride film has a first portion and a second portion. The first portion is provided between the charge storage portion and one of the metal layers. The second portion is thicker than the first portion and is provided between one of the metal layers and the insulator.

公开(公告)号：US20150262913A1

公开(公告)日：2015-09-17

申请号：US14484400

申请日：2014-09-12

Applicant: Kabushiki Kaisha Toshiba

Inventor： Satoshi WAKATSUKI ,  Atsuko SAKATA ,  Kengo UCHIDA ,  Kazuyuki HIGASHI ,  Mitsuyoshi ENDO

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/05541 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13009 ,  H01L2224/13011 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/206 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/1403

Abstract: A semiconductor device including a semiconductor substrate having a first surface and a second surface, the first surface being configured for formation of a semiconductor element; a through hole extending through the semiconductor substrate; and a through electrode disposed in the through hole. The through electrode includes an insulating film disposed along a sidewall of the through hole, a conductive layer comprising a first material disposed along the insulating film, and an electrode layer comprising a second material filled inside the through hole over the conductive layer. The first material is softer than the second material. The second material has a melting point higher than a melting point of the first material. The electrode layer includes a void portion being closed near the second surface of the semiconductor substrate.

Abstract translation: 一种半导体器件，包括具有第一表面和第二表面的半导体衬底，所述第一表面被配置为形成半导体元件; 穿过所述半导体衬底的通孔; 以及设置在通孔中的贯通电极。 贯通电极包括沿着通孔的侧壁设置的绝缘膜，包括沿着绝缘膜设置的第一材料的导电层和包含填充在导电层上方的通孔内的第二材料的电极层。 第一种材料比第二种材料柔软。 第二材料的熔点高于第一材料的熔点。 电极层包括在半导体衬底的第二表面附近封闭的空隙部分。

公开(公告)号：US20140284802A1

公开(公告)日：2014-09-25

申请号：US14022505

申请日：2013-09-10

Applicant: Kabushiki Kaisha Toshiba

Inventor： Atsuko SAKATA ,  Masayuki Kitamura ,  Makoto Wada ,  Masayuki Katagiri ,  Yuichi Yamazaki ,  Akihiro Kajita

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53276 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76852 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, a semiconductor device includes a metal interconnect and a graphene interconnect which are stacked to one another.

Abstract translation: 根据一个实施例，半导体器件包括彼此堆叠的金属互连和石墨烯互连。

公开(公告)号：US20140284801A1

公开(公告)日：2014-09-25

申请号：US14018645

申请日：2013-09-05

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Masayuki KITAMURA ,  Atsuko SAKATA ,  Takeshi ISHIZAKI ,  Satoshi WAKATSUKI

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53261 ,  H01L21/76877 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53257 ,  H01L27/105 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to an embodiment, a semiconductor device, includes a substrate, an inter-layer insulating layer provided above the substrate, a first interconnect provided in a first trench, and a second interconnect provided in a second trench. The first interconnect is made of a first metal, and the first trench is provided in the inter-layer insulating layer on a side opposite to the substrate. The second interconnect is made of a second metal, and the second trench is provided in the inter-layer insulating layer toward the substrate. A width of the second trench is wider than a width of the first trench. A mean free path of electrons in the first metal is shorter than a mean free path of electrons in the second metal, and the first metal is a metal, an alloy or a metal compound, including at least one nonmagnetic element as a constituent element.

Abstract translation: 根据实施例，半导体器件包括衬底，设置在衬底上的层间绝缘层，设置在第一沟槽中的第一互连以及设置在第二沟槽中的第二互连。 第一互连由第一金属制成，并且第一沟槽设置在与衬底相对的一侧的层间绝缘层中。 第二互连由第二金属制成，并且第二沟槽在层间绝缘层中朝向衬底提供。 第二沟槽的宽度比第一沟槽的宽度宽。 电子在第一金属中的平均自由程短于第二金属中电子的平均自由程，第一金属是包括至少一个非磁性元素作为构成元素的金属，合金或金属化合物。

公开(公告)号：US20140070417A1

公开(公告)日：2014-03-13

申请号：US14018637

申请日：2013-09-05

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Atsuko SAKATA ,  Takeshi ISHIZAKI

IPC: H01L23/532

CPC classification number: H01L23/4827 ,  H01L21/28061 ,  H01L21/28273 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/456 ,  H01L29/4941 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, a semiconductor device having an interlayer insulating film, a molybdenum containing layer, a barrier metal layer and a plug material layer is provided. The interlayer insulating film is formed on a substrate or on a conductive layer formed on a substrate. The interlayer insulating film has a hole reaching the substrate or the conductive layer. The molybdenum containing layer is formed in the substrate or in the conductive layer at a bottom portion of the hole. The barrier metal layer is formed on the molybdenum containing layer and on a side surface of the hole. A portion of the barrier metal layer is formed on the side surface contains at least molybdenum. A portion of the barrier metal layer is formed on the molybdenum containing layer includes at least a molybdenum silicate nitride film. The plug material layer is formed via the barrier metal layer.

Abstract translation: 根据一个实施例，提供了具有层间绝缘膜，含钼层，阻挡金属层和插塞材料层的半导体器件。 层间绝缘膜形成在基板上或形成在基板上的导电层上。 层间绝缘膜具有到达基板或导电层的孔。 含钼层在孔的底部形成在基板中或导电层中。 阻挡金属层形成在含钼层上和孔的侧面上。 阻挡金属层的一部分在侧面上形成至少含有钼。 所述阻挡金属层的一部分形成在所述含钼层上至少包含氮化钼硅酸盐膜。 插塞材料层通过阻挡金属层形成。

公开(公告)号：US20140070289A1

公开(公告)日：2014-03-13

申请号：US14016771

申请日：2013-09-03

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Masayuki TANAKA ,  Junichi WADA ,  Yoshio OZAWA ,  Koji YAMAKAWA ,  Seiji INUMIYA ,  Atsuko SAKATA

IPC: H01L43/10

CPC classification number: H01L43/10 ,  H01L27/1159 ,  H01L29/40111 ,  H01L29/513 ,  H01L29/516

Abstract: According to one embodiment, a ferroelectric memory includes a gate insulation film formed on a semiconductor substrate, a ferroelectric film formed on the gate insulation film, and a control electrode formed on the ferroelectric film. The ferroelectric film is a film containing a metal, which is hafnium or zirconium, and oxygen, and contains an element other than the metal at a concentration lower than a concentration of the metal.

Abstract translation: 根据一个实施例，铁电存储器包括形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的铁电膜以及形成在铁电体膜上的控制电极。 铁电体膜是含有铪或锆的金属和氧，并且含有浓度低于金属浓度的金属以外的元素的膜。

公开(公告)号：US20170170069A1

公开(公告)日：2017-06-15

申请号：US15131704

申请日：2016-04-18

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi WAKATSUKI ,  Hiroshi NAKAZAWA ,  Atsuko SAKATA

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53271 ,  H01L27/1157 ,  H01L27/11582

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a silicon film on an upper surface side, a lower surface side, and a side surface side of an air gap, while leaving part of the air gap between the silicon film formed on the upper surface side and the silicon film formed on the lower surface side. The method includes forming a metal film on a side surface of the slit. The method includes forming a plurality of metal silicide layers between the second layers by causing reaction between the metal film and the silicon film. The method includes removing unreacted part of the metal film formed on the side surface of the slit.