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公开(公告)号:US20130237008A1
公开(公告)日:2013-09-12
申请号:US13870424
申请日:2013-04-25
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Yasuhiro NOJIRI , Hiroyuki FUKUMIZU , Shinichi NAKAO , Kei WATANABE , Kazuhiko YAMAMOTO , Ichiro MIZUSHIMA , Yoshio OZAWA
IPC: H01L51/05
CPC classification number: H01L51/0591 , B82Y10/00 , B82Y40/00 , G11C13/0002 , G11C13/025 , G11C2213/71 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/149 , H01L45/1608
Abstract: According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film.
Abstract translation: 根据一个实施例,公开了一种用于制造非易失性存储器件的方法。 非易失性存储器件包括连接到第一互连和第二互连的存储单元。 该方法可以包括在第一互连上形成第一电极膜。 该方法可以包括在第一电极膜上形成分散在绝缘体内的多个碳纳米管的层。 多个碳纳米管中的至少一个碳纳米管从绝缘体的表面露出。 该方法可以包括在该层上形成第二电极膜。 另外,该方法可以包括在第二电极膜上形成第二互连。
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2.
公开(公告)号:US20170053869A1
公开(公告)日:2017-02-23
申请号:US14985969
申请日:2015-12-31
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Atsuko SAKATA , Takeshi ISHIZAKI , Shinya OKUDA , Kei WATANABE , Masayuki KITAMURA , Satoshi WAKATSUKI , Daisuke IKENO , Junichi WADA , Hirotaka OGIHARA
IPC: H01L23/522 , H01L23/532 , H01L21/3065 , H01L27/115 , H01L21/768
CPC classification number: H01L21/76879 , H01L21/3065 , H01L21/76843 , H01L21/76864 , H01L27/11582 , H01L29/7881
Abstract: According to one embodiment, the stacked body includes a plurality of metal films, a plurality of silicon oxide films, and a plurality of intermediate films. The intermediate films are provided between the metal films and the silicon oxide films. The intermediate films contain silicon nitride. Nitrogen composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the metal films than on sides of interfaces between the intermediate films and the silicon oxide films. Silicon composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the silicon oxide films than on sides of interfaces between the intermediate films and the metal films.
Abstract translation: 根据一个实施例,层叠体包括多个金属膜,多个氧化硅膜和多个中间膜。 中间膜设置在金属膜和氧化硅膜之间。 中间膜含有氮化硅。 在中间膜和金属膜之间的界面侧,中间膜的氮组成比在中间膜和氧化硅膜之间的界面侧更高。 在中间膜和氧化硅膜之间的界面侧,中间膜的硅组成比在中间膜和金属膜之间的界面侧更高。
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公开(公告)号:US20170092505A1
公开(公告)日:2017-03-30
申请号:US15376336
申请日:2016-12-12
Applicant: Kabushiki Kaisha Toshiba
Inventor: Shinichi NAKAO , Shunsuke OCHIAI , Yusuke OSHIKI , Kei WATANABE , Mitsuhiro OMURA , Kosuke HORIBE , Atsuko SAKATA , Junichi WADA , Soichi YAMAZAKI , Masayuki KITAMURA , Yuya MATSUBARA
IPC: H01L21/3065 , H01L27/11582 , H01L21/308
CPC classification number: H01L21/3065 , H01L21/3081 , H01L21/31144 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L27/11582 , H01L28/00
Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched, the mask layer containing tungsten and boron, a composition ratio of the tungsten being not less than 30%, patterning the mask layer, and performing a dry etching to the layer to be etched using the mask layer being patterned, and forming a hole or a slit in the layer to be etched.
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4.
公开(公告)号:US20160300845A1
公开(公告)日:2016-10-13
申请号:US14828830
申请日:2015-08-18
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Takeshi ISHIZAKI , Junichi WADA , Atsuko SAKATA , Kei WATANABE , Masayuki KITAMURA , Daisuke IKENO , Satoshi WAKATSUKl , Hirotaka OGIHARA , Shinya OKUDA
IPC: H01L27/115 , H01L27/02 , H01L21/28 , H01L29/423
CPC classification number: H01L27/11582 , H01L27/1157
Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a film having semi-conductivity or conductivity, and a memory film. The stacked body includes a plurality of metal layers, a plurality of insulating layers, and a plurality of intermediate layers stacked on a major surface of the substrate. The film extends in the stacked body in a stacking direction of the stacked body. The memory film is provided between the film and the metal layers. The metal layers are tungsten layers and the intermediate layers are tungsten nitride layers. Or the metal layers are molybdenum layers and the intermediate layers are molybdenum nitride layers.
Abstract translation: 根据一个实施例,半导体器件包括衬底,层叠体,具有半导电性或导电性的膜和存储膜。 堆叠体包括多个金属层,多个绝缘层和堆叠在基板的主表面上的多个中间层。 薄膜沿层叠体的层叠方向在层叠体上延伸。 记忆膜设置在膜和金属层之间。 金属层是钨层,中间层是氮化钨层。 或者金属层是钼层,中间层是氮化钼层。
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公开(公告)号:US20160276170A1
公开(公告)日:2016-09-22
申请号:US15064990
申请日:2016-03-09
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Shinya OKUDA , Kei WATANABE , Hidekazu HAYASHI
IPC: H01L21/322 , H01L21/311 , H01L21/02
CPC classification number: H01L21/02274 , H01L21/0206 , H01L21/02115 , H01L21/31111 , H01L21/32055
Abstract: A semiconductor manufacturing method in accordance with an embodiment includes feeding a first gas, which contains a component of a first film, to a reaction chamber, and forming a first film over a semiconductor substrate, which is accommodated in the reaction chamber, through plasma CVD. The semiconductor manufacturing method includes feeding a second gas to the reaction chamber after forming the first film, allowing the first gas in the reaction chamber to react on the second gas, and forming a second film, which has a composition different from that of the first film, over the surface of the first film. The semiconductor manufacturing method includes selectively removing the second film.
Abstract translation: 根据实施例的半导体制造方法包括将包含第一膜的成分的第一气体馈送到反应室,并且通过等离子体CVD将容纳在反应室中的半导体衬底上形成第一膜 。 半导体制造方法包括在形成第一膜之后将第二气体供给到反应室,使得反应室中的第一气体在第二气体上反应,并形成第二膜,其具有与第一膜不同的组成 电影,在第一部电影的表面。 半导体制造方法包括选择性地去除第二膜。
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公开(公告)号:US20170062459A1
公开(公告)日:2017-03-02
申请号:US15001991
申请日:2016-01-20
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Yasuhito YOSHIMIZU , Akifumi GAWASE , Kei WATANABE , Shinya ARAI
IPC: H01L27/115 , H01L21/28 , H01L29/06 , H01L21/768 , H01L21/764 , H01L23/535 , H01L29/423 , H01L21/306
CPC classification number: H01L27/11582 , H01L21/764 , H01L23/53295
Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a second air gap, a first insulating film, a semiconductor film, and a stacked film. The stacked body is provided above the substrate and includes a plurality of electrode films stacked via a first air gap. The second air gap extends in a stacking direction of the stacked body. The second air gap separates the stacked body in a first direction crossing the stacking direction. The first insulating film is provided above the stacked body and covers an upper end of the second air gap. The stacked film is provided between a side surface of the electrode film and a side surface of the semiconductor film opposed to the side surface of the electrode film. The stacked film is in contact with the side surface of the electrode film and the side surface of the semiconductor film.
Abstract translation: 根据一个实施例,半导体器件包括衬底,层叠体,第二气隙,第一绝缘膜,半导体膜和堆叠膜。 层叠体设置在基板上方,并且包括经由第一气隙堆叠的多个电极膜。 第二气隙在层叠体的堆叠方向上延伸。 第二气隙沿与层叠方向交叉的第一方向分离。 第一绝缘膜设置在层叠体的上方并覆盖第二气隙的上端。 叠层膜设置在电极膜的侧表面和与电极膜的侧表面相对的半导体膜的侧表面之间。 层叠膜与电极膜的侧面和半导体膜的侧面接触。
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公开(公告)号:US20160064649A1
公开(公告)日:2016-03-03
申请号:US14639689
申请日:2015-03-05
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Kei WATANABE
CPC classification number: H01L43/02 , H01L27/228 , H01L43/08
Abstract: According to one embodiment, a magnetic memory device includes a stack structure including a first magnetic layer, a nonmagnetic layer and a second magnetic layer, a protection insulating film covering at least a side surface of the stack structure, and an intermediate insulating film provided between the stack structure and the protection insulating film, and containing silicon (Si), carbon (C) and hydrogen (H).
Abstract translation: 根据一个实施例,一种磁存储器件包括:堆叠结构,包括第一磁性层,非磁性层和第二磁性层,覆盖该堆叠结构的至少侧面的保护绝缘膜,和 堆叠结构和保护绝缘膜,并含有硅(Si),碳(C)和氢(H)。
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