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公开(公告)号：US08318574B2
公开(公告)日：2012-11-27
申请号：US12847208
申请日：2010-07-30
IPC分类号： H01L21/20
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having of a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, where the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion of the top silicon layer, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.
摘要翻译： 在一个示例性实施例中，一种半导体结构，包括：具有覆盖绝缘层的顶部硅层的SOI衬底，所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在所述顶部硅层上的器件，其中所述器件耦合到所述顶部硅层的掺杂部分; 第一外延沉积材料的背面带，背侧带的至少第一部分位于顶部硅层的掺杂部分的下面，背面带在背面的第一端耦合到顶部硅层的掺杂部分 带子和背部带子的第二端处的电容器; 以及至少部分地覆盖在顶部硅层的掺杂部分上的第二外延沉积材料，第二外延沉积材料还至少部分地覆盖在第一部分上。
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公开(公告)号：US20120286350A1
公开(公告)日：2012-11-15
申请号：US13558518
申请日：2012-07-26
申请人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
IPC分类号： H01L29/78
CPC分类号： H01L21/26586 , H01L29/665 , H01L29/66636 , H01L29/66659 , H01L29/78
摘要： An FET device characterized as being an asymmetrical tunnel FET (TFET) is disclosed. The TFET includes a gate-stack, a channel region underneath the gate-stack, a first and a second junction adjoining the gate-stack and being capable for electrical continuity with the channel. The first junction and the second junction are of different conductivity types. The TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side.
摘要翻译： 公开了一种以不对称隧道FET（TFET）为特征的FET器件。 TFET包括栅极堆叠，栅极堆叠下方的沟道区域，邻接栅极叠层的第一和第二结，并且能够与沟道电连接。 第一接头和第二接头具有不同的导电类型。 TFET还包括间隔物结构，使得栅极叠层的一侧上的间隔物形成比另一侧更薄。
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3.发明申请STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER 有权具有单个间距的垂直源/源压应力的应变薄体CMOS器件公开(公告)号：US20120261757A1
公开(公告)日：2012-10-18
申请号：US13531053
申请日：2012-06-22
IPC分类号： H01L29/78 , H01L27/092
CPC分类号： H01L29/66477 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66772 , H01L29/7848 , H01L29/78618
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.
摘要翻译： 一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一 在图案化的栅极结构下方的半导体衬底的沟道区上。
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公开(公告)号：US20120049284A1
公开(公告)日：2012-03-01
申请号：US12861976
申请日：2010-08-24
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L27/1211 , H01L27/1203
摘要： In one exemplary embodiment, a semiconductor structure includes: a semiconductor-on-insulator substrate with a top semiconductor layer overlying an insulation layer and the insulation layer overlies a bottom substrate layer; at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion has a first thickness, a first width and a first depth; and at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion has a second thickness, a second width and a second depth, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth.
摘要翻译： 在一个示例性实施例中，半导体结构包括：绝缘体上半导体衬底，具有覆盖绝缘层的顶部半导体层，绝缘层覆盖在底部衬底层上; 至少一个第一装置至少部分地覆盖并设置在顶部半导体层的第一部分上，其中第一部分具有第一厚度，第一宽度和第一深度; 以及至少一个第二装置，其至少部分地覆盖并设置在顶部半导体层的第二部分上，其中第二部分具有第二厚度，第二宽度和第二深度，其中以下至少一个成立：第一 厚度大于第二厚度，第一宽度大于第二宽度，第一深度大于第二深度。
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5.发明申请STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER 有权具有单个间距的垂直源/源压应力的应变薄体CMOS器件公开(公告)号：US20110309446A1
公开(公告)日：2011-12-22
申请号：US12816399
申请日：2010-06-16
IPC分类号： H01L27/12 , H01L21/8238 , H01L29/786 , H01L21/336
CPC分类号： H01L29/66477 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66772 , H01L29/7848 , H01L29/78618
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.
摘要翻译： 一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一 在图案化的栅极结构下方的半导体衬底的沟道区上。
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公开(公告)号：US20110254080A1
公开(公告)日：2011-10-20
申请号：US12760287
申请日：2010-04-14
申请人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/665 , H01L29/66636 , H01L29/66659 , H01L29/78
摘要： A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack.
摘要翻译： 公开了一种用于制造FET器件的方法，其特征在于是隧道FET（TFET）器件。 该方法包括处理栅极堆叠，以及处理第一导电类型的邻接的源极和漏极结。 形成覆盖栅极堆叠和结的硬掩模。 执行由硬掩模的第一部分接收的倾斜角度离子注入，并且由于栅极堆叠的阴影而不被硬掩模的第二部分接收。 去除硬掩模的注入部分，并露出其中一个接头。 该结被蚀刻掉，并且通常原位掺杂到第二导电类型的新结，外延生长到其位置。 还公开了一种特征为不对称TFET的器件。 TFET的源极和漏极结具有不同的导电类型，并且TFET还包括间隔物结构，使得栅极堆叠的一侧上的间隔物形成比栅极堆叠的另一侧更薄。
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公开(公告)号：US08022488B2
公开(公告)日：2011-09-20
申请号：US12566004
申请日：2009-09-24
IPC分类号： H01L21/02
CPC分类号： H01L29/7848 , H01L21/2257 , H01L21/26586 , H01L29/165 , H01L29/41775 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a first epitaxy semiconductor material that induces a strain upon a channel of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.
摘要翻译： 提供了高性能半导体结构和制造这种结构的方法。 半导体结构包括位于半导体衬底的上表面上的至少一个栅堆叠，例如FET。 该结构还包括在至少一个栅极堆叠的沟道上引起应变的第一外延半导体材料。 第一外延半导体材料位于至少一个栅极堆叠的基准面上，基本上位于衬底中的存在于至少一个栅极堆叠的相对侧上的一对凹陷区域内。 扩散扩展区域位于每个凹陷区域中的所述第一外延半导体材料的上表面内。 该结构还包括位于扩散扩展区的上表面上的第二外延半导体材料。 第二外延半导体材料具有比第一外延半导体材料更高的掺杂剂浓度。
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公开(公告)号：US09054211B2
公开(公告)日：2015-06-09
申请号：US13540801
申请日：2012-07-03
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/785
摘要： An FET device structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.
摘要翻译： FET器件结构具有具有Si基材料的翅片的Fin-FET器件。 氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。 另外的FET器件结构具有Fin-FET器件。 垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。
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9.发明授权Extremely thin semiconductor-on-insulator (ETSOI) integrated circuit with on-chip resistors and method of forming the same 有权具有片上电阻的非常薄的绝缘体上半导体（ETSOI）集成电路及其形成方法公开(公告)号：US08629504B2
公开(公告)日：2014-01-14
申请号：US13433401
申请日：2012-03-29
IPC分类号： H01L21/00
CPC分类号： H01L27/1214 , H01L21/84 , H01L27/1203 , H01L27/13
摘要： An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided.
摘要翻译： 提供了一种电气装置，其在一个实施例中包括具有厚度小于10nm的半导体层的绝缘体上半导体（SOI）基板。 在半导体层的第一表面上存在具有第一导电性的单晶半导体材料的升高的源极区域和升高的漏极区域的半导体器件。 由第一导电性的单晶半导体材料构成的电阻器存在于半导体层的第二表面上。 还提供了形成上述电气装置的方法。
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公开(公告)号：US08587086B2
公开(公告)日：2013-11-19
申请号：US13598992
申请日：2012-08-30
IPC分类号： H01L21/70
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/76283 , H01L27/1104
摘要： FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer.
摘要翻译： 提供了FDSOI器件及其制造方法。 一方面，一种制造装置的方法包括以下步骤。 提供具有基板，BOX和SOI层的晶片。 硬掩模层沉积在SOI层上。 光致抗蚀剂层沉积在硬掩模层上并且被图案化成一组片段。 执行倾斜的植入物以损坏被片段覆盖或遮蔽的硬掩模层的所有部分。 移除由植入物损坏的硬掩模层的部分。 通过硬掩模层执行第一蚀刻，以在SOI层，BOX和衬底的至少一部分中形成深沟槽。 使用图案化的光致抗蚀剂层对硬掩模层进行图案化。 通过硬掩模层进行第二蚀刻，以在SOI层中形成浅沟槽。
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