公开(公告)号：US20160005739A1

公开(公告)日：2016-01-07

申请号：US14738814

申请日：2015-06-12

Applicant: KILHO LEE ,  SHINHEE HAN

Inventor： KILHO LEE ,  SHINHEE HAN

IPC: H01L27/105 ,  H01L23/528 ,  H01L21/28 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L29/423

CPC classification number: H01L21/76877 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/4236 ,  H01L29/66621 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A semiconductor memory device includes a first insulating layer covering a substrate, a first contact plug and a second contact plug each penetrating the first insulating layer, a first data storage element disposed on the first contact plug, and a second data storage element disposed on the second contact plug. The first contact plug includes a vertically extending portion and a horizontally extending portion arranged between the vertically extending portion and the first data storage element, and the second contact plug extends substantially vertically from a top surface of the substrate. The first data storage element is laterally spaced apart from the vertically extending portion when viewed in plan view. The first data storage element is disposed on the horizontally extending portion.

Abstract translation: 半导体存储器件包括覆盖基片的第一绝缘层，每个穿透第一绝缘层的第一接触插塞和第二接触插塞，设置在第一接触插塞上的第一数据存储元件和设置在第一绝缘层上的第二数据存储元件 第二个接触插头 第一接触插塞包括垂直延伸部分和布置在垂直延伸部分和第一数据存储元件之间的水平延伸部分，并且第二接触插塞从衬底的顶表面基本垂直地延伸。 当在平面图中观察时，第一数据存储元件与垂直延伸部分横向间隔开。 第一数据存储元件设置在水平延伸部分上。

公开(公告)号：US20170324025A1

公开(公告)日：2017-11-09

申请号：US15436757

申请日：2017-02-17

Applicant: KILHO LEE ,  Kiseok SUH ,  Yoonsung HAN ,  GWANHYEOB KOH ,  YOONJONG SONG

Inventor： KILHO LEE ,  Kiseok SUH ,  Yoonsung HAN ,  GWANHYEOB KOH ,  YOONJONG SONG

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

Abstract: A data storage device and a method for manufacturing the data storage device provide a data storage device having a superior reliability and easy fabrication. The data storage device comprises a substrate including cell and peripheral circuit regions, a first conductive line on the peripheral circuit region, a peripheral contact plug between the substrate and the first conductive line, the peripheral contact plug being in contact with the first conductive line, a second conductive line on the cell region, a plurality of data storage structures between the substrate and the second conductive line, and a wiring structure between the substrate and each of the data storage structures and between the substrate and the peripheral contact plug. The first conductive line includes a bottom surface having a position from the substrate that is lower than a position of a bottom surface of the second conductive line.

公开(公告)号：US20150017742A1

公开(公告)日：2015-01-15

申请号：US14226770

申请日：2014-03-26

Applicant: KILHO LEE

Inventor： KILHO LEE

IPC: H01L21/768 ,  H01L27/22

CPC classification number: H01L21/76816 ,  H01L27/228

Abstract: Methods for manufacturing a data storage device are provided. A method may include forming an interlayer dielectric layer on a substrate, patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches, forming first bit lines in the first trenches, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches after the formation of the first bit lines, and forming second bit lines in the second trenches.

Abstract translation: 提供了用于制造数据存储装置的方法。 一种方法可以包括在衬底上形成层间电介质层，在衬底的周边区域中形成层间电介质层以形成第一沟槽，在第一沟槽中形成第一位线，将第一位线之间的层间介质层图形化 所述外围区域形成在形成所述第一位线之后沿着所述第一沟槽延伸的第二沟槽，以及在所述第二沟槽中形成第二位线。

公开(公告)号：US20180159023A1

公开(公告)日：2018-06-07

申请号：US15622064

申请日：2017-06-13

Applicant: Kiseok SUH ,  BYOUNGJAE BAE ,  GWANHYEOB KOH ,  YOONJONG SONG ,  KILHO LEE

Inventor： Kiseok SUH ,  BYOUNGJAE BAE ,  GWANHYEOB KOH ,  YOONJONG SONG ,  KILHO LEE

IPC: H01L43/02 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08

Abstract: A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.

公开(公告)号：US20150228321A1

公开(公告)日：2015-08-13

申请号：US14526489

申请日：2014-10-28

Applicant: KILHO LEE ,  SANGYONG KIM ,  WOOJIN KIM ,  KyungTae NAM

Inventor： KILHO LEE ,  SANGYONG KIM ,  WOOJIN KIM ,  KyungTae NAM

IPC: G11C11/16

CPC classification number: G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/221

Abstract: A magnetic memory device is provided. The magnetic memory device includes a plurality of variable resistance devices connected to a word line, and a plurality of bit lines, each of which provides an electrical pathway between a corresponding one of the variable resistance devices and a read and write circuit. Each of the variable resistance devices includes a free layer and a pinned layer spaced apart from each other and having a tunnel barrier interposed therebetween, an assistant layer spaced apart from the tunnel barrier and having the free layer interposed therebetween, and an exchange coupling layer arranged between the free layer and the assistant layer. The exchange coupling layer has an electric polarization, which results from its ferroelectric property, and having a direction that can be changed by a voltage applied to the corresponding one of the bit lines.

Abstract translation: 提供磁存储器件。 磁存储器件包括连接到字线的多个可变电阻器件和多个位线，每个位线提供相应的一个可变电阻器件与读写电路之间的电路径。 每个可变电阻装置包括自由层和钉扎层，彼此间隔开并具有插入其间的隧道势垒，辅助层与隧道势垒间隔开并且具有插入其间的自由层，并且布置有交换耦合层 在自由层和辅助层之间。 交换耦合层具有由其铁电性质产生的电极化，并且具有可以通过施加到相应的一个位线的电压而改变的方向。

公开(公告)号：US20140042508A1

公开(公告)日：2014-02-13

申请号：US13951328

申请日：2013-07-25

Applicant: KILHO LEE

Inventor： KILHO LEE

IPC: H01L27/22 ,  H01L29/78

CPC classification number: H01L27/228 ,  H01L27/11585 ,  H01L29/78

Abstract: A semiconductor memory device includes a cell gate dielectric layer and a cell gate electrode disposed in a gate recess region crossing a cell active portion of a substrate, first and second doped regions disposed in the cell active portion at both sides of the gate recess region, respectively, at least one interlayer insulating layer covering the substrate, a data storage element electrically connected to the second doped region through a contact plug penetrating the at least one interlayer insulating layer, a mold layer covering the data storage element, and a bit line disposed in a cell groove formed in the mold layer. The bit line is in direct contact with a top surface of the data storage element.

Abstract translation: 半导体存储器件包括：单元栅极电介质层和设置在与衬底的单元有源部分交叉的栅极凹部区域中的单元栅极电极，设置在栅极凹部区域两侧的单元有源部分中的第一和第二掺杂区域， 覆盖基板的至少一个层间绝缘层，通过穿透至少一个层间绝缘层的接触插塞电连接到第二掺杂区域的数据存储元件，覆盖数据存储元件的模具层和布置的位线 在模具层中形成的电池槽中。 位线与数据存储元件的顶表面直接接触。