公开(公告)号：US20240311286A1

公开(公告)日：2024-09-19

申请号：US18601791

申请日：2024-03-11

Applicant: Kioxia Corporation

Inventor： Atsushi KAWASUMI ,  Takashi MAEDA ,  Hidehiro SHIGA

IPC: G06F12/02 ,  G11C16/04 ,  G11C16/26

CPC classification number: G06F12/02 ,  G11C16/0483 ,  G11C16/26 ,  G06F2212/10

Abstract: An information processing apparatus that detects whether the corresponding first element and second element among the multiple first elements and the plurality of second elements are matched or are similar, has one or multiple strings connected to a first wiring and connected to multiple second wirings, wherein the string includes multiple transistor pairs connected in series along a current path having one end connected to the first wiring, each of the multiple transistor pairs includes a first transistor and a second transistor connected in series along the current path, the second wirings are connected to gates of the first transistor and the second transistor in each of the multiple transistor pairs, the first transistor is set to a first threshold depending on first data, the second transistor is set to a second threshold depending on second data that is complement data of the first data.

公开(公告)号：US20220302923A1

公开(公告)日：2022-09-22

申请号：US17471887

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Atsushi KAWASUMI

IPC: H03M1/20 ,  G11C7/16 ,  G11C7/22

Abstract: A semiconductor integrated circuit has a digital signal generator that generates a binary signal whose logic transitions at a timing according to a discharge amount of a second wiring which is discharged when multiplication data of first data stored in a memory cell and second data on a first wiring is a first logic; and a transition timing detector that detects a timing at which the logic of the binary signal transitions.

公开(公告)号：US20220084601A1

公开(公告)日：2022-03-17

申请号：US17338987

申请日：2021-06-04

Applicant: Kioxia Corporation

Inventor： Atsushi KAWASUMI

IPC: G11C16/12 ,  G11C16/30 ,  H03K5/14 ,  G11C16/08 ,  G11C7/10 ,  H03K19/21 ,  G11C16/26

Abstract: A semiconductor memory device according to an embodiment includes a peripheral circuit part supplied with a first voltage, a core circuit part supplied with a second voltage greater than the first voltage, a pre-decoder provided in the peripheral circuit part, input with a signal and outputting a one-hot signal corresponding to the signal, a first wiring provided in the peripheral circuit part, electrically connected to the pre-decoder, and supplied with the one-hot signal, a second wiring provided in the core circuit part, a level shifter provided in the peripheral circuit part, supplied with a first voltage and a second voltage, and transferring the one-hot signal from the first wiring in the peripheral circuit part to the second wiring in the core circuit part, and a memory cell array provided in the core circuit part and operating based on the transferred one-hot signal.

公开(公告)号：US20220076743A1

公开(公告)日：2022-03-10

申请号：US17348005

申请日：2021-06-15

Applicant: Kioxia Corporation

Inventor： Takeshi SUGIMOTO ,  Atsushi KAWASUMI

IPC: G11C13/00

Abstract: According to the embodiment, in a first period, the semiconductor storage device maintains the switch in an ON state. In a second period, the semiconductor storage device performs a first operation, a second operation and a third operation while maintaining the switch in an OFF state. The second period is a period after the first period. The first operation is an operation to supply the first pulse having the first polarity from the first pulse generation circuit to the other end of the first capacitive element. The second operation is an operation to supply the second pulse having the second polarity from the second pulse generation circuit to the other end of the second capacitive element. The third operation is an operation to connect the first bit line to the first data line.

公开(公告)号：US20250077617A1

公开(公告)日：2025-03-06

申请号：US18822608

申请日：2024-09-03

Applicant: Kioxia Corporation

Inventor： Atsushi KAWASUMI

IPC: G06F17/16

Abstract: An information processing apparatus includes a first positive wiring line carrying a current of a multiplication value of a first integer element and a second integer element when the multiplication value is zero or more, a first negative wiring line carrying a current of the multiplication value when the multiplication value is zero or less, a second positive wiring line activated when the second integer element is positive, a second negative wiring line activated when the second integer element is negative, a first calculator carrying the current through the first positive wiring line when the multiplication value is zero or more, a second calculator carrying the current through the first negative wiring line, a third calculator caused the current to flow through the first positive wiring line when the multiplication value is zero or more, and a fourth calculator caused the current to flow through the first negative wiring line.

公开(公告)号：US20240427843A1

公开(公告)日：2024-12-26

申请号：US18743892

申请日：2024-06-14

Applicant: Kioxia Corporation

Inventor： Atsushi KAWASUMI

IPC: G06F17/16

Abstract: An information processing apparatus configured to detect similarity between a first vector having a plurality of elements and a second vector having a plurality of elements based on an inner product value of the first vector and the second vector, the information processing apparatus has a wiring line having a current flowing therethrough, the current being a sum of currents each corresponding to a product of a value obtained by subtracting one of the elements of the first vector from a reference value and a corresponding one of the elements of the second vector, a sense amplifier configured to sense a voltage on the wiring line, and a similarity detection circuit configured to detect the similarity based on an output signal of the sense amplifier.

公开(公告)号：US20220301597A1

公开(公告)日：2022-09-22

申请号：US17471909

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Atsushi KAWASUMI

IPC: G11C5/06 ,  G11C11/417 ,  G11C11/412 ,  G06F7/544

Abstract: A semiconductor integrated circuit has a plurality of memory cells arranged in a first direction and each storing first data, a plurality of first wirings provided to correspond to the plurality of memory cells arranged in the first direction and supplying second data to be multiplied by the first data, and a second wiring pair provided to correspond to the plurality of memory cells arranged in the first direction and that includes one second wiring which is discharged when multiplication data of the first data, stored in each of the plurality of memory cells, and the second data, supplied by the first wiring corresponding to the memory cell, is a first logic; and another second wiring which is discharged when the multiplication data is a second logic.

公开(公告)号：US20220084588A1

公开(公告)日：2022-03-17

申请号：US17345208

申请日：2021-06-11

Applicant: Kioxia Corporation

Inventor： Kazuki OKAWA ,  Hiroyuki HARA ,  Atsushi KAWASUMI

IPC: G11C13/00 ,  G11C5/06 ,  H03K19/173

Abstract: Provided is a semiconductor storage device including: a substrate having a substrate surface extending in a first direction and a second direction intersecting the first direction; a plurality of first region memory cells provided in a plurality of layers provided parallel to the substrate surface and in a third direction, the first region memory cells being provided above a rectangular shaped first region provided on the substrate surface, the first region having a first side parallel to the first direction and a second side parallel to the second direction when viewed from the third direction intersecting the first direction and the second direction; a plurality of first region wirings provided between the first region memory cells; a plurality of second region memory cells provided in the layers, the second region memory cells being provided above a rectangular shaped second region having a third side parallel to the first direction and a fourth side parallel to the second direction when viewed from the third direction; a plurality of second region wirings provided between the second region memory cells; and a control circuit capable of executing a reading operation, wherein, in the reading operation, the control circuit performs reading from one of the first region memory cells provided in one of the layers and another one of the second region memory cells provided in another one of the layers.

公开(公告)号：US20220084581A1

公开(公告)日：2022-03-17

申请号：US17197371

申请日：2021-03-10

Applicant: Kioxia Corporation

Inventor： Atsushi KAWASUMI

IPC: G11C11/4094 ,  G11C11/4097 ,  G11C5/06 ,  G06F7/544 ,  G06N3/08 ,  G06N3/063

Abstract: A semiconductor storage device has a plurality of memory cells that are arranged in a first direction and store first data, a plurality of first wiring pairs that are provided corresponding to the plurality of memory cells arranged in the first direction, and supply second data multiplied with the first data, a second wiring pair that is provided corresponding to two memory cells adjacent to each other in the first direction, and outputs multiplication data obtained by multiplying the first data stored in the two memory cells with the corresponding second data on the first wiring pair, and a third wiring pair in which potentials are changed depending on an addition result only when the addition result obtained by adding two multiplication data output to the second wiring pair to each other is not zero.

公开(公告)号：US20210295904A1

公开(公告)日：2021-09-23

申请号：US17199650

申请日：2021-03-12

Applicant: Kioxia Corporation

Inventor： Atsushi KAWASUMI

IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11

Abstract: A semiconductor memory device of an embodiment includes: a first inverter including a first P-channel and first N-channel transistors; a second inverter including a second P-channel and second N-channel transistors and being cross-connected to the first inverter; a third P-channel transistor; a third N-channel transistor; a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; a sixth wiring; and a controller that drives the first to sixth wirings. When writing second-level data that is at a higher potential level than first-level data into the drain of the second P-channel transistor and the drain of the second N-channel transistor, the controller puts one of the fifth wiring and the sixth wiring into a floating state.