公开(公告)号：US11747979B2

公开(公告)日：2023-09-05

申请号：US17235144

申请日：2021-04-20

Applicant: Kioxia Corporation

Inventor： Tetsuya Sunata ,  Daisuke Iwai ,  Kenichiro Yoshii

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1044 ,  G06F2212/2022

Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.

公开(公告)号：US11609844B2

公开(公告)日：2023-03-21

申请号：US16806173

申请日：2020-03-02

Applicant: KIOXIA CORPORATION

Inventor： Keiri Nakanishi ,  Konosuke Watanabe ,  Kohei Oikawa ,  Daisuke Iwai

IPC: G06F12/02 ,  G06F13/16

Abstract: A memory system includes a first memory that is nonvolatile, a second memory that is volatile, and a memory controller. The memory controller is configured to store first information in the second memory. The first information includes management information. The memory controller is further configured to compress the first information. The compressed first information is second information. The memory controller is configured to store the second information in the first memory.

公开(公告)号：US11847050B2

公开(公告)日：2023-12-19

申请号：US17184313

申请日：2021-02-24

Applicant: KIOXIA CORPORATION

Inventor： Daisuke Iwai ,  Toshio Fujisawa ,  Keigo Hara

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0238 ,  G06F2212/202 ,  G06F2212/403 ,  G06F2212/7205

Abstract: According to one embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit stores data read from a first position of the memory chip in a memory when a first command for compaction is received from a controller, transmits validity determination information used for determining whether or not the data read from the first position is valid to the controller, and writes valid data of the data stored in the memory to a second position of the memory chip when a second command for the compaction and validity identification information that identifies the valid data are received from the controller.

公开(公告)号：US11520496B2

公开(公告)日：2022-12-06

申请号：US17108311

申请日：2020-12-01

Applicant: Kioxia Corporation

Inventor： Daisuke Iwai ,  Kenichiro Yoshii ,  Tetsuya Sunata

IPC: G06F3/06

Abstract: According to one embodiment, an electronic device connectable to a host via an interface includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory and capable of processing commands issued by the host in parallel. When the electronic device is connected to the host, the controller determines, when one or more commands to be processed by one or more deadline times, respectively, are issued by the host, scheduling indicative of timings at which the one or more commands are processed, respectively, based on the one or more deadline times. The controller performs processing corresponding to the one or more commands in accordance with the scheduling.

公开(公告)号：US11307797B2

公开(公告)日：2022-04-19

申请号：US16290633

申请日：2019-03-01

Applicant: Kioxia Corporation

Inventor： Tetsuya Sunata ,  Daisuke Iwai ,  Kenichiro Yoshii

IPC: G06F3/06 ,  G06F12/02

Abstract: According to one embodiment, a storage device is accessible by an external device via an interface and includes a nonvolatile memory including one or more blocks, and a controller electrically connected to the nonvolatile memory. The controller receives from the external device a request and a notification indicating that a response performance of the request is to be lowered. In response to receiving the request and notification, the controller determines a response time longer than a processing time of the request, and executes a first performance lowering process that executes a block managing process of the nonvolatile memory by using an idle time which is a difference between the response time and the processing time of the request or executes a second performance lowering process that lowers the response performance so as to process the request by spending the response time.