公开(公告)号：US11923325B2

公开(公告)日：2024-03-05

申请号：US17695654

申请日：2022-03-15

Applicant: Kioxia Corporation

Inventor： Yasuhito Yoshimizu ,  Takashi Fukushima ,  Tatsuro Hitomi ,  Arata Inoue ,  Masayuki Miura ,  Shinichi Kanno ,  Toshio Fujisawa ,  Keisuke Nakatsuka ,  Tomoya Sanuki

IPC: H01L23/00 ,  G06F11/07 ,  H01L23/544

CPC classification number: H01L24/05 ,  G06F11/073 ,  G06F11/0751 ,  H01L23/544 ,  H01L2223/5446 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2924/14511

Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.

公开(公告)号：US11942176B2

公开(公告)日：2024-03-26

申请号：US17475482

申请日：2021-09-15

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Xu Li ,  Masayuki Miura ,  Takayuki Miyazaki ,  Toshio Fujisawa ,  Hiroto Nakai ,  Hideko Mukaida ,  Mie Matsuo

IPC: G11C5/00 ,  G11C5/14 ,  G11C16/30 ,  H02M3/158 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C5/14 ,  G11C16/30 ,  H02M3/1582 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.

公开(公告)号：US11868285B2

公开(公告)日：2024-01-09

申请号：US17990169

申请日：2022-11-18

Applicant: Kioxia Corporation

Inventor： Toshio Fujisawa ,  Nobuhiro Kondo ,  Shoji Sawamura ,  Kenichi Maeda ,  Atsushi Kunimatsu

IPC: G06F13/16 ,  G06F13/28 ,  G11C11/00 ,  G11C5/04

CPC classification number: G06F13/1668 ,  G06F13/28 ,  G11C11/005 ,  G11C5/04

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.

公开(公告)号：US11847050B2

公开(公告)日：2023-12-19

申请号：US17184313

申请日：2021-02-24

Applicant: KIOXIA CORPORATION

Inventor： Daisuke Iwai ,  Toshio Fujisawa ,  Keigo Hara

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0238 ,  G06F2212/202 ,  G06F2212/403 ,  G06F2212/7205

Abstract: According to one embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit stores data read from a first position of the memory chip in a memory when a first command for compaction is received from a controller, transmits validity determination information used for determining whether or not the data read from the first position is valid to the controller, and writes valid data of the data stored in the memory to a second position of the memory chip when a second command for the compaction and validity identification information that identifies the valid data are received from the controller.

公开(公告)号：US11537536B2

公开(公告)日：2022-12-27

申请号：US17155415

申请日：2021-01-22

Applicant: Kioxia Corporation

Inventor： Toshio Fujisawa ,  Nobuhiro Kondo ,  Shoji Sawamura ,  Kenichi Maeda ,  Atsushi Kunimatsu

IPC: G06F13/16 ,  G06F13/28 ,  G11C11/00 ,  G11C5/04

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.

公开(公告)号：US12204765B2

公开(公告)日：2025-01-21

申请号：US18181824

申请日：2023-03-10

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Toshio Fujisawa ,  Keisuke Nakatsuka

IPC: G06F12/00 ,  G06F3/06

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and a memory controller. The nonvolatile semiconductor storage device includes at least one memory device including a plurality of memory cells corresponding to a plurality of pages. The memory controller is configured to control the nonvolatile semiconductor storage device. The pages include a first page. The memory controller is configured to: read first data stored in the first page from the nonvolatile semiconductor storage device; correct a fail bit included in the read first data; generate first spare data including information on the fail bit corrected in the read first data; and store the first spare data in the nonvolatile semiconductor storage device.

公开(公告)号：US12142324B2

公开(公告)日：2024-11-12

申请号：US17681547

申请日：2022-02-25

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Sanuki ,  Keisuke Nakatsuka ,  Daisuke Fujiwara ,  Toshio Fujisawa

IPC: G11C16/08 ,  G11C8/12 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34

Abstract: A semiconductor storage device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory strings, a plurality of word lines, each of which is connected to the memory strings, and a plurality of bit lines connected to the memory strings, respectively. The plurality of bit lines are grouped into a plurality of bit line groups. The control circuit is configured to receive a read command and first address information specifying one or more of the bit line groups. The control circuit is configured to, in response to the read command, read data selectively from each memory string connected to each bit line in the one or more bit line groups specified by the first address information, and output the read data.

公开(公告)号：US11579796B2

公开(公告)日：2023-02-14

申请号：US17197667

申请日：2021-03-10

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Yuta Aiba ,  Hitomi Tanaka ,  Masayuki Miura ,  Mie Matsuo ,  Toshio Fujisawa ,  Takashi Maeda

IPC: G06F3/00 ,  G06F3/06

Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of −40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of −40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.

公开(公告)号：US11756946B2

公开(公告)日：2023-09-12

申请号：US17847528

申请日：2022-06-23

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Sanuki ,  Toshio Fujisawa ,  Hiroshi Maejima ,  Takashi Maeda

IPC: G11C16/04 ,  H01L25/18 ,  H01L23/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G06F3/06

CPC classification number: H01L25/18 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  G11C16/0483 ,  H01L2224/13016 ,  H01L2224/16057 ,  H01L2224/16145 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/73207

Abstract: A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.

公开(公告)号：US20230078983A1

公开(公告)日：2023-03-16

申请号：US17990169

申请日：2022-11-18

Applicant: Kioxia Corporation

Inventor： Toshio Fujisawa ,  Nobuhiro Kondo ,  Shoji Sawamura ,  Kenichi Maeda ,  Atsushi Kunimatsu

IPC: G06F13/16 ,  G06F13/28 ,  G11C11/00

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.