公开(公告)号：US12183398B2

公开(公告)日：2024-12-31

申请号：US17897695

申请日：2022-08-29

Applicant: Kioxia Corporation

Inventor： Keigo Hara

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

Abstract: A memory system includes a memory controller and a semiconductor storage device. The semiconductor storage device performs a program operation of performing a software program loop including applying a write voltage to a word line, performing program verification for performing write determination of a first data value, and increasing a set value of the write voltage if determining that writing of the first data value is not completed, and generates an index based on first information obtained according to a progress of writing the first data value in the program operation. The memory controller determines whether to perform read verification of reading data from the plurality of memory cells based on the index.

公开(公告)号：US20230197159A1

公开(公告)日：2023-06-22

申请号：US17897695

申请日：2022-08-29

Applicant: Kioxia Corporation

Inventor： Keigo Hara

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C16/3459

Abstract: A memory system includes a memory controller and a semiconductor storage device. The semiconductor storage device performs a program operation of performing a software program loop including applying a write voltage to a word line, performing program verification for performing write determination of a first data value, and increasing a set value of the write voltage if determining that writing of the first data value is not completed, and generates an index based on first information obtained according to a progress of writing the first data value in the program operation. The memory controller determines whether to perform read verification of reading data from the plurality of memory cells based on the index.

公开(公告)号：US11568074B2

公开(公告)日：2023-01-31

申请号：US16549506

申请日：2019-08-23

Applicant: Kioxia Corporation

Inventor： Keigo Hara

IPC: G06F21/62 ,  G06F3/06 ,  G06F11/10

Abstract: According to one embodiment, a memory system is connectable to a host including a first volatile memory and includes a non-volatile memory and a controller. The controller may use a first area of the first volatile memory as a temporary storage memory of data stored in the non-volatile memory and controls the non-volatile memory. The controller generates a first parity by using first data stored in the non-volatile memory and a key value to store the first data and the generated first parity in the first area. In the case of reading the first data stored in the first area, the controller reads the first data and the first parity to verify the read first data using the read first parity and the key value.

公开(公告)号：US11847050B2

公开(公告)日：2023-12-19

申请号：US17184313

申请日：2021-02-24

Applicant: KIOXIA CORPORATION

Inventor： Daisuke Iwai ,  Toshio Fujisawa ,  Keigo Hara

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0238 ,  G06F2212/202 ,  G06F2212/403 ,  G06F2212/7205

Abstract: According to one embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit stores data read from a first position of the memory chip in a memory when a first command for compaction is received from a controller, transmits validity determination information used for determining whether or not the data read from the first position is valid to the controller, and writes valid data of the data stored in the memory to a second position of the memory chip when a second command for the compaction and validity identification information that identifies the valid data are received from the controller.