-
公开(公告)号：US20220285391A1
公开(公告)日：2022-09-08
申请号：US17412933
申请日：2021-08-26
Applicant: Kioxia Corporation
Inventor： Kazuharu YAMABE , Yoshiro SHIMOJO
IPC: H01L27/11582
Abstract: In a method for manufacturing a memory, a first stacked body is formed by stacking a first insulating film and a first sacrificial film. A first columnar body including a first semiconductor portion extending in the first stacked body in the first direction and a charge trapping film provided on an outer peripheral surface of the first semiconductor portion is formed. A second columnar body provided in a second direction of the first columnar body and including a second semiconductor portion stretching in the first stacked body in the first direction and a charge trapping film on an outer peripheral surface of the second semiconductor portion is formed. A second insulating film is formed above the first stacked body. A third columnar body including a third semiconductor portion provided on both the first columnar body and the second columnar body and stretching in the second insulating film in the first direction and a first gate insulating film provided on an outer peripheral surface of the third semiconductor portion is formed. A first division insulating film extending in the first direction and a third direction intersecting the first direction and the second direction and dividing the third semiconductor portion of the third columnar body in the second direction is formed.
-
公开(公告)号：US20240315058A1
公开(公告)日：2024-09-19
申请号：US18595321
申请日：2024-03-04
Applicant: Kioxia Corporation
Inventor： Go OIKE , Kazuharu YAMABE
IPC: H10B80/00 , H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18
CPC classification number: H10B80/00 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
Abstract: A semiconductor memory device includes a first cell chip and a second cell chip. The first cell chip includes a first stack, a first conductive layer that is used as a first source line, a second conductive layer that is electrically connected to the first conductive layer, and a plurality of first bonding pads. The second cell chip includes a second stack, a third conductive layer that is used as a second source line, a plurality of second bonding pads that are joined to the plurality of first bonding pads, respectively, and a fourth conductive layer that electrically couples the plurality of second bonding pads and is electrically connected to the third conductive layer. The second conductive layer and the fourth conductive layer are electrically connected.
-
公开(公告)号：US20230397414A1
公开(公告)日：2023-12-07
申请号：US18177010
申请日：2023-03-01
Applicant: Kioxia Corporation
Inventor： Takeshi MURATA , Kazuharu YAMABE
IPC: H10B41/27 , H01L23/522 , H01L23/528 , H10B41/10 , H10B43/10 , H10B43/27
CPC classification number: H10B41/27 , H01L23/5226 , H01L23/5283 , H10B41/10 , H10B43/10 , H10B43/27
Abstract: A semiconductor device includes a substrate, and a stacked film provided above the substrate and including a plurality of electrode layers separated from each other in a first direction. The device further includes an array region provided on the substrate and including a memory cell array having a plurality of word lines and a plurality of select lines that constitute the plurality of electrode layers. The device further includes a first plug region provided on the substrate, located in a second direction of the array region, and including a first contact plug electrically connected to a first select line of the plurality of select lines. The device further includes a second plug region provided on the substrate, located in the second direction of the first plug region, and including a second contact plug electrically connected to a first word line of the plurality of word lines.
-
Patent Agency Ranking
公开(公告)号：US20210264984A1
公开(公告)日：2021-08-26
申请号：US17315079
申请日：2021-05-07
Applicant: KIOXIA CORPORATION
Inventor： Kazuharu YAMABE , Qianqian XU
Abstract: A memory device includes a first cell above a substrate, a first line connected to the first cell, a second cell above the first cell connected with the first cell, a second line connected to the second cell, a third cell above the second cell connected with the second cell, a third line connected to the third cell, a fourth cell above the third cell connected with the third cell, a fourth line connected to the fourth cell, and a driver applying voltages to the lines when data is written to a cell in a write operation. To write data to the second cell, the driver applies a write voltage to the second line, applies a first voltage lower than the write voltage to the first line, and applies a second voltage higher than the first voltage and lower than the write voltage to the third and fourth lines.
-
公开(公告)号：US20210280256A1
公开(公告)日：2021-09-09
申请号：US16993509
申请日：2020-08-14
Applicant: Kioxia Corporation
Inventor： Kazuharu YAMABE , Yoichi MINEMURA
Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, first and second word lines, and a bit line. The first and second memory cells are coupled to each other and adjacent to each other. When a state of the second memory cell is the first state or one of the states corresponding to a lower threshold voltage distribution than that of the first state, the first memory cell data is read in a first period during which a first voltage is applied to the second word line. And when the state of the second memory cell is the second state or one of the states corresponding to a higher threshold voltage distribution than the second state, the first memory cell data is read in a second period during which a second voltage higher than the first voltage is applied to the second word line.
-
公开(公告)号：US20210082512A1
公开(公告)日：2021-03-18
申请号：US16808187
申请日：2020-03-03
Applicant: KIOXIA CORPORATION
Inventor： Kazuharu YAMABE , Qianqian XU
Abstract: A memory device includes a first cell above a substrate, a first line connected to the first cell, a second cell above the first cell connected with the first cell, a second line connected to the second cell, a third cell above the second cell connected with the second cell, a third line connected to the third cell, a fourth cell above the third cell connected with the third cell, a fourth line connected to the fourth cell, and a driver applying voltages to the lines when data is written to a cell in a write operation. To write data to the second cell, the driver applies a write voltage to the second line, applies a first voltage lower than the write voltage to the first line, and applies a second voltage higher than the first voltage and lower than the write voltage to the third and fourth lines.
-
公开(公告)号：US20240422971A1
公开(公告)日：2024-12-19
申请号：US18814868
申请日：2024-08-26
Applicant: Kioxia Corporation
Inventor： Kazuharu YAMABE
Abstract: A semiconductor storage device includes a substrate, a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate, a first semiconductor layer that extends in the first direction and faces the plurality of first conductive layers, a first gate insulating film that extends in the first direction and covers an outer peripheral surface of the first semiconductor layer, a first insulating layer that extends in the first direction and has an outer peripheral surface covered with the first semiconductor layer, and a second conductive layer that is farther from the substrate than the plurality of first conductive layers and is connected to one end in the first direction of the first semiconductor layer. The first semiconductor layer includes a first region facing the plurality of first conductive layers and a second region farther from the substrate than the first region. The second conductive layer is connected to an inner peripheral surface and an outer peripheral surface of the second region of the first semiconductor layer and is in contact with one end in the first direction of the first insulating layer.
-
公开(公告)号：US20220068949A1
公开(公告)日：2022-03-03
申请号：US17190739
申请日：2021-03-03
Applicant: Kioxia Corporation
Inventor： Kazuharu YAMABE
IPC: H01L27/11578 , H01L27/11519 , H01L27/11526 , H01L27/11551 , H01L27/11573 , H01L27/11565 , H01L23/00
Abstract: A semiconductor storage device includes a substrate, a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate, a first semiconductor layer that extends in the first direction and faces the plurality of first conductive layers, a first gate insulating film that extends in the first direction and covers an outer peripheral surface of the first semiconductor layer, a first insulating layer that extends in the first direction and has an outer peripheral surface covered with the first semiconductor layer, and a second conductive layer that is farther from the substrate than the plurality of first conductive layers and is connected to one end in the first direction of the first semiconductor layer. The first semiconductor layer includes a first region facing the plurality of first conductive layers and a second region farther from the substrate than the first region. The second conductive layer is connected to an inner peripheral surface and an outer peripheral surface of the second region of the first semiconductor layer and is in contact with one end in the first direction of the first insulating layer.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.028 seconds)
