公开(公告)号：US20250054521A1

公开(公告)日：2025-02-13

申请号：US18928444

申请日：2024-10-28

Applicant: KIOXIA CORPORATION

Inventor： Masato SUGITA ,  Naoki KIMURA ,  Daisuke KIMURA

IPC: G11C5/04 ,  G06F13/42 ,  G06F16/9535 ,  G11C5/02 ,  G11C5/06 ,  G11C14/00 ,  G11C16/04

Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

公开(公告)号：US20230343371A1

公开(公告)日：2023-10-26

申请号：US18347517

申请日：2023-07-05

Applicant: KIOXIA CORPORATION

Inventor： Masato SUGITA ,  Naoki KIMURA ,  Daisuke KIMURA

IPC: G11C5/04 ,  G06F16/9535 ,  G11C5/06 ,  G11C5/02 ,  G11C16/04 ,  G11C14/00 ,  G06F13/42

CPC classification number: G11C5/04 ,  G06F16/9535 ,  G11C5/06 ,  G11C5/02 ,  G11C16/04 ,  G11C5/063 ,  G11C14/0018 ,  G06F13/4282 ,  G06F2213/0032

Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

公开(公告)号：US20220122640A1

公开(公告)日：2022-04-21

申请号：US17565713

申请日：2021-12-30

Applicant: Kioxia Corporation

Inventor： Masato SUGITA ,  Naoki KIMURA ,  Daisuke KIMURA

IPC: G11C5/04 ,  G06F16/9535 ,  G11C5/06 ,  G11C5/02 ,  G11C16/04 ,  G11C14/00 ,  G06F13/42

Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.