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    MEMORY SYSTEM AND CONTROL METHOD
    1.
    发明公开
    MEMORY SYSTEM AND CONTROL METHOD 审中-公开

    公开(公告)号：US20240087657A1

    公开(公告)日：2024-03-14

    申请号：US18179310

    申请日：2023-03-06

    Applicant: Kioxia Corporation

    Inventor： Yohei EGUCHI ,  Naoki KIMURA

    IPC: G11C16/30 ,  G11C16/04

    CPC classification number: G11C16/30 ,  G11C16/0483

    Abstract: According to one embodiment, a memory system includes a nonvolatile memory to store data, a memory controller configured to perform data operations on the nonvolatile member, and a power circuit configured to receive external power and generate internal power to be supplied to the nonvolatile memory and the memory controller. The memory controller is further configured to receive a request signal for disabling supply of the internal power for a first time period and disable the supply of the internal power from the power circuit in response to the request signal after a second time period elapses after reception of the request signal. The second time period is shorter than the first time period. The supply of the internal power from the power circuit resumes after the first time period elapses after the reception of the request signal.

    MEMORY SYSTEM AND METHOD OF CONTROLLING THEREOF
    2.
    发明申请
    MEMORY SYSTEM AND METHOD OF CONTROLLING THEREOF 有权

    公开(公告)号：US20220291868A1

    公开(公告)日：2022-09-15

    申请号：US17469486

    申请日：2021-09-08

    Applicant: Kioxia Corporation

    Inventor： Naoki KIMURA ,  Junya KISHIKAWA

    IPC: G06F3/06 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F1/10

    Abstract: A memory system of an embodiment is connectable to a host and includes a nonvolatile memory and a memory controller. The memory controller includes: a signal line which transfers a signal sent from the host; a resistance element disposed between and electrically connected to the signal line and a wiring line given a reference potential of the memory system; a switching element connected serially to the resistance element and capable of switching a connection between the signal line and the wiring line; and a control circuit which controls the switching element to switch the connection between the signal line and the wiring line from a connected state to a disconnected state, when a change from a first potential to a second potential occurs on the signal line or when a change from the second potential to the first potential occurs on the signal line.

    MEMORY SYSTEM
    5.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20220139469A1

    公开(公告)日：2022-05-05

    申请号：US17578244

    申请日：2022-01-18

    Applicant: KIOXIA CORPORATION

    Inventor： Naoki KIMURA

    IPC: G11C16/30 ,  G01R19/165 ,  H02H3/20 ,  G11C5/14 ,  G06F1/30

    Abstract: A memory system includes a connector through which power for the memory system is to be supplied from an external device, a controller, a nonvolatile memory device, a power source circuit connected to the controller and the nonvolatile memory device by power lines through which power is supplied to the controller and the nonvolatile memory device, and a power source control circuit that receives a supply of power from the external device through the connector and supplies the power to the power control circuit. The power source control circuit is configured to detect using a divided voltage of a voltage of the power supplied thereto, that the voltage of the power supplied thereto is higher than a predetermined voltage and interrupt the power supplied to the power control circuit if the voltage of the power supplied thereto is higher than the predetermined voltage.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220122640A1

    公开(公告)日：2022-04-21

    申请号：US17565713

    申请日：2021-12-30

    Applicant: Kioxia Corporation

    Inventor： Masato SUGITA ,  Naoki KIMURA ,  Daisuke KIMURA

    IPC: G11C5/04 ,  G06F16/9535 ,  G11C5/06 ,  G11C5/02 ,  G11C16/04 ,  G11C14/00 ,  G06F13/42

    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

    MEMORY SYSTEM
    8.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20230307065A1

    公开(公告)日：2023-09-28

    申请号：US17896828

    申请日：2022-08-26

    Applicant: Kioxia Corporation

    Inventor： Naoki KIMURA

    IPC: G11C16/30 ,  G11C16/04

    CPC classification number: G11C16/30 ,  G11C16/0483

    Abstract: A memory system includes: a connector including a first terminal and a second terminal, each of which is capable of being connected to a host device; a non-volatile memory; and a controller connected between the connector and the non-volatile memory. The controller includes: a control circuit including a first node and a second node; a first signal line connected between the first terminal and the first node and capable of being pulled up to a first power level or a second power level; a second signal line connected to the second terminal; and a first resistance element including one end connected to the first signal line and the other end connected to the second signal line.

    STORAGE SYSTEM
    9.
    发明申请
    STORAGE SYSTEM 有权

    公开(公告)号：US20220302661A1

    公开(公告)日：2022-09-22

    申请号：US17472382

    申请日：2021-09-10

    Applicant: Kioxia Corporation

    Inventor： Kazuyuki MATSUZAKI ,  Naoki KIMURA

    IPC: H01R25/00 ,  H01R12/73 ,  H01R12/70 ,  H05K1/14

    Abstract: According to one embodiment, a storage system includes a circuit board, a connector, a first memory system, and a second memory system. The connector is on the circuit board and includes first and second slots, the first slot having a first terminal group of first terminals aligned in a first direction, and the second slot being separated from the first slot in a second direction not parallel with the first direction and having a second terminal group of second terminals aligned in the first direction. The first terminal group is reverse to the second terminal group in terminal arrangement order in the first direction. The first memory system is connectable to the first terminal group, while the first memory system is inserted into the first slot. The second memory system is connectable to the second terminal group, while the second memory system is inserted into the second slot.

    MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM
    10.
    发明申请
    MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM 有权

    公开(公告)号：US20210286743A1

    公开(公告)日：2021-09-16

    申请号：US17004877

    申请日：2020-08-27

    Applicant: KIOXIA CORPORATION

    Inventor： Naoki KIMURA

    IPC: G06F13/16

    Abstract: A memory system includes a connector including a terminal, and a controller configured to perform a single-line bidirectional communication with a host via a signal line connected to the terminal. A format of a signal communicated via the single-line bidirectional communication includes a start pulse at a first level, a stop pulse at a second level, data pulses at the second level, and division pulses at the first level. The data pulses are after the start pulse but before the stop pulse. Each of the data pulses has a pulse width corresponding to a data value represented thereby. The division pulses have a uniform pulse width. A pulse width of the start pulse is greater than the uniform pulse width of the divisional pulses. A pulse width of the stop pulse is greater than any pulse width of the data pulses.

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