公开(公告)号：US20240061620A1

公开(公告)日：2024-02-22

申请号：US18501943

申请日：2023-11-03

Applicant: Kioxia Corporation

Inventor： Takeshi NAKANO ,  Akihiko ISHIHARA ,  Shingo TANIMOTO ,  Yasuaki NAKAZATO ,  Shinji MAEDA ,  Minoru UCHIDA ,  Kenji SAKAUE ,  Koichi INOUE ,  Yosuke KINO ,  Takumi SASAKI ,  Mikio TAKASUGI ,  Kouji SAITOU ,  Hironori NAGAI ,  Shinya TAKEDA ,  Akihito TOUHATA ,  Masaru OGAWA ,  Akira AOKI

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F11/1068

Abstract: A memory system includes a non-volatile memory and a controller that includes a first memory and is configured to write log data to the first memory, including a history of commands for controlling the memory system. An information processing system includes the memory system and an information processing device configured to store an expected value and to transmit a signal that instructs the memory system to stop when a value of the log data transmitted from the memory system does not match the expected value. The expected value and the transmitted value are determined based on the log data of the memory system.

公开(公告)号：US20240143531A1

公开(公告)日：2024-05-02

申请号：US18458249

申请日：2023-08-30

Applicant: Kioxia Corporation

Inventor： Koichi INOUE ,  Sachiyo MIYAMOTO ,  Minoru UCHIDA ,  Taro IWASHIRO ,  Kenji SAKAUE

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F2213/28

Abstract: A memory system includes a nonvolatile memory and a memory controller including a bus, a cache memory, a direct memory access controller, a first search circuit, a second search circuit, and a transfer control circuit. The direct memory access controller transfers cache target data stored in the nonvolatile memory to the cache memory. The second search circuit searches the cache target data that is being transferred. The transfer control circuit assigns, in response to the second search circuit detecting a search hit, to the transfer control circuit and the second search circuit, a bus right which has been assigned at least to the cache memory for the transfer of the cache target data to the cache memory, and obtains, by using the assigned bus right, a search result from the second search circuit via the bus.

公开(公告)号：US20210303214A1

公开(公告)日：2021-09-30

申请号：US17185104

申请日：2021-02-25

Applicant: KIOXIA CORPORATION

Inventor： Takeshi NAKANO ,  Akihiko ISHIHARA ,  Shingo TANIMOTO ,  Yasuaki NAKAZATO ,  Shinji MAEDA ,  Minoru UCHIDA ,  Kenji SAKAUE ,  Koichi INOUE ,  Yosuke KINO ,  Takumi SASAKI ,  Mikio TAKASUGI ,  Kouji SAITOU ,  Hironori NAGAI ,  Shinya TAKEDA ,  Akihito TOUHATA ,  Masaru OGAWA ,  Akira AOKI

IPC: G06F3/06 ,  G06F11/10

Abstract: A memory system includes a non-volatile memory and a controller that includes a first memory and is configured to write log data to the first memory, including a history of commands for controlling the memory system. An information processing system includes the memory system and an information processing device configured to store an expected value and to transmit a signal that instructs the memory system to stop when a value of the log data transmitted from the memory system does not match the expected value. The expected value and the transmitted value are determined based on the log data of the memory system.