公开(公告)号：US20210296166A1

公开(公告)日：2021-09-23

申请号：US17003123

申请日：2020-08-26

Applicant: Kioxia Corporation

Inventor： Hiroshi YOSHIMURA ,  Kazuyuki HINO ,  Jiro HIGUCHI ,  Sachiyo ITO ,  Ken FURUBAYASHI

IPC: H01L21/768 ,  G06F30/398

Abstract: In general, according to one embodiment, a stress analysis method comprising: dividing a surface of an object into a plurality of first rectangles each having a first size, on data; and acquiring a first type value for each of the first rectangles. The method further includes: specifying, from among the first rectangles, a plurality of second rectangles that have the first type value of a magnitude that falls within a first range and form a rectangle; and generating a stress model for a set of the second rectangles by using the second rectangles as an element.

公开(公告)号：US20240057338A1

公开(公告)日：2024-02-15

申请号：US18176525

申请日：2023-03-01

Applicant: Kioxia Corporation

Inventor： Wataru HASEGAWA ,  Takuya KONNO ,  Sachiyo ITO ,  Ken FURUBAYASHI

IPC: H10B43/35 ,  H10B43/10 ,  H10B43/27 ,  H01L23/522 ,  H01L23/528

CPC classification number: H10B43/35 ,  H10B43/10 ,  H10B43/27 ,  H01L23/5226 ,  H01L23/5283

Abstract: According to one embodiment, a memory device includes: a first layer stack including first insulating layers arranged in a first direction and spaced apart from one another; second and third layer stacks, each including conductive layers spaced apart from one another and provided at levels of layers identical to the first insulating layers, respectively, and being spaced apart from each other; a memory pillar extending in the first direction in the third layer stack, a portion of the memory pillar intersecting each of the conductive layers functioning as a memory cell; a first member in contact with the first and second layer stacks between the first and second layer stacks and extending in a second direction; and a second member in contact with the second and third layer stacks between the second and third layer stacks and extending in the second direction.

公开(公告)号：US20230317632A1

公开(公告)日：2023-10-05

申请号：US17883690

申请日：2022-08-09

Applicant: Kioxia Corporation

Inventor： Mayuka OJIMA ,  Sachiyo ITO ,  Takuya KONNO

IPC: H01L23/00 ,  H01L23/58 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device according to an embodiment includes a substrate, a transistor, an insulating layer, and a first sealing portion. The substrate includes a first region, and a second region provided to surround an outer periphery of the first region. The transistor is provided on the substrate in the first region. The insulating layer is provided above the transistor and over the first region and the second region. The first sealing portion is provided to divide the insulating layer and surround the outer periphery of the first region in the second region. The first sealing portion includes a first void.

公开(公告)号：US20230062835A1

公开(公告)日：2023-03-02

申请号：US17679896

申请日：2022-02-24

Applicant: KIOXIA CORPORATION

Inventor： Takuya KONNO ,  Sachiyo ITO

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: According to one embodiment, a semiconductor device includes a first substrate, a second substrate joined to the first substrate. A first region of the semiconductor device that includes a peripheral circuit is between the first substrate and the second substrate. A second region that includes a memory cell array is between the first region and the second substrate. A layer that is embedded in the second substrate has a Young's modulus that is higher than that of silicon and/or an internal stress that is higher than that of silicon oxide.

公开(公告)号：US20220384363A1

公开(公告)日：2022-12-01

申请号：US17680126

申请日：2022-02-24

Applicant: KIOXIA CORPORATION

Inventor： Ken FURUBAYASHI ,  Sachiyo ITO ,  Takuya KONNO

IPC: H01L23/00 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor storage device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked along a stacking direction, and a plurality of first pillars extending in the stacked body along the stacking direction to form memory cells at intersections with at least some of the plurality of conductive layers. The stacked body includes a stair portion in which the plurality of conductive layers are stacked in a stepped manner at a position separated from the plurality of first pillars in a first direction intersecting the stacking direction. At least a lowermost insulating layer of the plurality of insulating layers has at least one bending portion bent in the stacking direction at an end of the plurality of conductive layers in the stair portion along the first direction.