公开(公告)号：US12223236B2

公开(公告)日：2025-02-11

申请号：US17193546

申请日：2021-03-05

Applicant: KABUSHIKI KAISHA TOSHIBA ,  Kioxia Corporation

Inventor： Daiki Kiribuchi ,  Satoru Yokota ,  Soh Koike ,  Tadayoshi Uechi

IPC: G06F30/20 ,  G06F17/18 ,  G06N7/01 ,  G06F111/10

Abstract: An information processing apparatus according to an embodiment of the present invention includes an estimator and a recommender. The estimator is configured to, based on a data set including a set value set for a parameter and an evaluation value or an evaluation value variation where the set value is set for the parameter, estimate a relationship between the set value and the evaluation value variation. The evaluation value variation indicates a variation of respective evaluation values where a plurality of values included within a neighborhood range that is based on the set value are set for the parameter. The recommender is configured to, based on the estimated relationship, determine a recommended set value.

公开(公告)号：US11694995B2

公开(公告)日：2023-07-04

申请号：US17188308

申请日：2021-03-01

Applicant: Kioxia Corporation

Inventor： Michihito Kono ,  Takashi Izumida ,  Tadayoshi Uechi ,  Takeshi Shimane

IPC: H10B43/40 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40 ,  H01L2224/08145 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device, includes: a first region including a memory cell array; and a second region including a peripheral circuit. The second region includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes: a semiconductor region between the first and second surfaces; an n-type semiconductor region provided on the first surface and higher in donor concentration than the semiconductor region; a damaged region provided on the second surface; and a p-type semiconductor region provided between the damaged region and the n-type semiconductor region, closer to the second surface than the n-type semiconductor region in a direction from the first surface toward the second surfaces of the semiconductor substrate, and higher in acceptor concentration than the semiconductor region.

公开(公告)号：US11616072B2

公开(公告)日：2023-03-28

申请号：US17656143

申请日：2022-03-23

Applicant: Kioxia Corporation

Inventor： Tetsuya Yamashita ,  Takuyo Nakayama ,  Takashi Ichikawa ,  Tadayoshi Uechi ,  Takashi Izumida

IPC: H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11578

Abstract: According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.

公开(公告)号：US11527645B2

公开(公告)日：2022-12-13

申请号：US16526025

申请日：2019-07-30

Applicant: KIOXIA CORPORATION

Inventor： Tadayoshi Uechi ,  Takashi Izumida ,  Takeshi Shimane

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08

Abstract: A semiconductor device of an embodiment includes: a first and second semiconductor regions of a first conductivity type; a third semiconductor region of a second conductivity type disposed between the first and second semiconductor regions; a fourth semiconductor region of the first conductivity type disposed below the first semiconductor region; a fifth semiconductor region of the first conductivity type disposed below the second semiconductor region; a first region containing carbon disposed between the first and fourth semiconductor regions; a second region containing carbon disposed between the second and fifth semiconductor regions; a third region disposed between the first and second regions; the first and second regions having a first and second carbon concentrations respectively, the third region not containing carbon or having a lower carbon concentration than the first and second carbon concentrations in a portion below an end of a lower face of a gate electrode.

公开(公告)号：US11355510B2

公开(公告)日：2022-06-07

申请号：US16801312

申请日：2020-02-26

Applicant: Kioxia Corporation

Inventor： Tetsuya Yamashita ,  Takuyo Nakayama ,  Takashi Ichikawa ,  Tadayoshi Uechi ,  Takashi Izumida

IPC: H01L27/11575 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11578

Abstract: According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.