公开(公告)号：US11705210B2

公开(公告)日：2023-07-18

申请号：US17570676

申请日：2022-01-07

Applicant: Kioxia Corporation

Inventor： Akio Sugahara ,  Takaya Handa ,  Ryosuke Isomura ,  Kazuto Uehara ,  Junichi Sato ,  Norichika Asaoka ,  Masashi Yamaoka ,  Bushnaq Sanad ,  Yuzuru Shibazaki ,  Noriyasu Kumazaki ,  Yuri Terada

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/12 ,  H10B69/00

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/32 ,  G11C16/12 ,  G11C16/26 ,  H10B69/00

Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.

公开(公告)号：US11114170B2

公开(公告)日：2021-09-07

申请号：US16886546

申请日：2020-05-28

Applicant: KIOXIA CORPORATION

Inventor： Takaya Handa ,  Yoshihisa Kojima ,  Kiyotaka Iwasaki

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/32 ,  G11C16/24 ,  G11C7/10 ,  G11C7/22

Abstract: A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.

公开(公告)号：US12159677B2

公开(公告)日：2024-12-03

申请号：US18205915

申请日：2023-06-05

Applicant: Kioxia Corporation

Inventor： Akio Sugahara ,  Takaya Handa ,  Ryosuke Isomura ,  Kazuto Uehara ,  Junichi Sato ,  Norichika Asaoka ,  Masashi Yamaoka ,  Bushnaq Sanad ,  Yuzuru Shibazaki ,  Noriyasu Kumazaki ,  Yuri Terada

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/32 ,  G11C16/12 ,  G11C16/26 ,  H10B69/00

Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.