公开(公告)号：US11876080B2

公开(公告)日：2024-01-16

申请号：US17860830

申请日：2022-07-08

Applicant: KIOXIA CORPORATION

Inventor： Masahiro Yoshihara ,  Toshikazu Watanabe ,  Nobuharu Miyata ,  Yasumitsu Nozawa ,  Tomohito Kawano ,  Sachie Fukuda ,  Akiyoshi Itou ,  Toshimitsu Iwasawa

IPC: H01L25/065 ,  H01L23/00 ,  G11C16/30 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08

CPC classification number: H01L25/0657 ,  H01L24/06 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  H01L2224/06165 ,  H01L2224/09165 ,  H01L2224/4813 ,  H01L2224/48105 ,  H01L2224/4911 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/14511 ,  H01L2924/182

Abstract: A semiconductor memory device includes first and second memory chips, each including a region of a core circuit, a first area adjacent to a first side of the region in a first direction, a second area adjacent to a second side of the region in a second direction, a third area adjacent to the first area in the first direction and to the second area in the second direction, a first pad in the first area, a second pad in the second area, and third pad in the third area. In each memory chip, a first bonding wire connects the first and third pads. In addition, a second bonding wire connects the second pads of the first and second memory chips. The second memory chip is stacked on the first memory chip to expose the first, second, and third areas of the first memory chip in a third direction.

公开(公告)号：US11410974B2

公开(公告)日：2022-08-09

申请号：US17011487

申请日：2020-09-03

Applicant: KIOXIA CORPORATION

Inventor： Masahiro Yoshihara ,  Toshikazu Watanabe ,  Nobuharu Miyata ,  Yasumitsu Nozawa ,  Tomohito Kawano ,  Sachie Fukuda ,  Akiyoshi Itou ,  Toshimitsu Iwasawa

IPC: H01L25/065 ,  H01L23/00 ,  G11C16/30 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08

Abstract: A semiconductor memory device includes first and second memory chips, each including a region of a core circuit, a first area adjacent to a first side of the region in a first direction, a second area adjacent to a second side of the region in a second direction, a third area adjacent to the first area in the first direction and to the second area in the second direction, a first pad in the first area, a second pad in the second area, and third pad in the third area. In each memory chip, a first bonding wire connects the first and third pads. In addition, a second bonding wire connects the second pads of the first and second memory chips. The second memory chip is stacked on the first memory chip to expose the first, second, and third areas of the first memory chip in a third direction.