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    METHOD AND SYSTEM OF TRAINING SPIKING NEURAL NETWORK BASED CONVERSION AWARE TRAINING
    1.
    发明公开
    METHOD AND SYSTEM OF TRAINING SPIKING NEURAL NETWORK BASED CONVERSION AWARE TRAINING 审中-公开

    公开(公告)号：US20240112024A1

    公开(公告)日：2024-04-04

    申请号：US18449188

    申请日：2023-08-14

    Applicant: Korea University Research and Business Foundation

    Inventor： Jongsun PARK ,  Dongwoo LEW ,  Kyung Chul LEE

    IPC: G06N3/08

    CPC classification number: G06N3/08

    Abstract: Disclosed are a spiking neural network training method based the conversion aware training and a system thereof. The spiking neural network training method includes an ANN generation operation of generating an analog artificial neural network (ANN) model and inputting variable data, a conversion aware training operation of simulating a spiking neural network (SNN) model by using one or more activation functions with respect to the analog ANN model, and an SNN generation operation of generating the SNN model by correcting parameters and weights of layers based on a result of the simulation.

    Supervised training accelerator for temporal coding-based spiking neural network and operation method thereof
    2.
    发明公开
    Supervised training accelerator for temporal coding-based spiking neural network and operation method thereof 审中-公开

    公开(公告)号：US20230237318A1

    公开(公告)日：2023-07-27

    申请号：US18099628

    申请日：2023-01-20

    Applicant: Korea University Research and Business Foundation

    Inventor： Jongsun PARK ,  Sung Hyun CHOI ,  Dongwoo LEW

    IPC: G06N3/049 ,  G06V10/774

    CPC classification number: G06N3/049 ,  G06V10/774

    Abstract: Disclosed are a method for accelerating supervised training of a spiking neural network. The method includes measuring first and second membrane potentials for each time step during a training process, extracting distribution data of the first and second membrane potentials based on the first and second membrane potentials for the each time step, calculating a threshold value to be used in a subsequent training process based on the distribution data of the first and second membrane potentials, classifying images having no training contribution based on the threshold value calculated in a previous training process, and terminating the training at the time step based on determining that the image does not have the training contribution when a difference between the first and second membrane potentials in the time step is greater than the threshold value.

    NONVOLATILE RESISTIVE MEMORY DEVICE USING DYNAMIC REFERENCE IN DUAL DOMAIN AND READ METHOD THEREOF
    4.
    发明申请
    NONVOLATILE RESISTIVE MEMORY DEVICE USING DYNAMIC REFERENCE IN DUAL DOMAIN AND READ METHOD THEREOF 有权

    公开(公告)号：US20230138195A1

    公开(公告)日：2023-05-04

    申请号：US17961116

    申请日：2022-10-06

    Applicant: Korea University Research and Business Foundation

    Inventor： Jongsun PARK ,  Joo Yoon KIM

    IPC: G06F3/06

    Abstract: Disclosed is a method of reading a nonvolatile resistive memory device including a data cell and a reference cell. The method includes precharging a first bit line connected to the data cell and a second bit line connected to the reference cell, discharging a voltage precharged to the first bit line and the second bit line to a source node through the data cell and the reference cell, sampling a reference voltage developed to the second bit line at a first time when a voltage of the first bit line reaches a threshold voltage, sampling a data voltage developed to the first bit line at a second time when a voltage of the second bit line reaches the threshold voltage, and sensing and amplifying a difference value between the reference voltage and the data voltage and outputting the sensed and amplified difference value as output data.

    SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL
    8.
    发明公开
    SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL 审中-公开

    公开(公告)号：US20240257852A1

    公开(公告)日：2024-08-01

    申请号：US18423980

    申请日：2024-01-26

    Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION

    Inventor： Jongsun PARK ,  TaeHwan KIM

    IPC: G11C11/16

    CPC classification number: G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    Abstract: The semiconductor device includes a first memory cell, a second memory cell disposed adjacent to the first memory cell along a first direction, a first bit line extending in a second direction perpendicular to the first direction and connected to the first memory cell, a second bit line and a third bit line extending in the second direction between the first memory cell and the second memory cell and connected to the first memory cell and the second memory cell, and a control unit connected to the first bit line, the second bit line, and the third bit line. The control unit performs a read operation on the first memory cell by using the first bit line and performs a write operation on the first memory cell or the second memory cell by using the second bit line and the third bit line.

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