公开(公告)号：US08502316B2

公开(公告)日：2013-08-06

申请号：US12704367

申请日：2010-02-11

申请人： Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

发明人： Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

IPC分类号： H01L29/72

CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate.

摘要翻译： 集成电路结构包括包括有源区的半导体衬底。 第一浅沟槽隔离（STI）区域邻接有源区域的第一侧。 MOS器件的栅电极在有源区和第一STI区之上。 MOS器件的源极/漏极应力区域包括半导体衬底中的与栅电极相邻的部分。 在半导体衬底中形成沟槽，并与有源区域的第二面相邻。 沟槽的底部不低于源极/漏极区域的底部。 层间电介质（ILD）从栅极电极延伸到沟槽内部，其中沟槽中的ILD的一部分形成第二STI区域。 第二STI区域和源极/漏极应力区域彼此分离并邻接半导体衬底的一部分。

公开(公告)号：US20110193179A1

公开(公告)日：2011-08-11

申请号：US12716100

申请日：2010-03-02

申请人： Ka-Hing Fung ,  Haiting Wang ,  Han-Ting Tsai

发明人： Ka-Hing Fung ,  Haiting Wang ,  Han-Ting Tsai

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7848

摘要： An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The method involves providing a substrate; forming a gate structure over the substrate; forming an epitaxial layer in a source and drain region of the substrate that is interposed by the gate structure; and after forming the epitaxial layer, forming a lightly doped source and drain (LDD) feature in the source and drain region.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 该方法包括提供基底; 在衬底上形成栅极结构; 在由栅极结构插入的衬底的源极和漏极区域中形成外延层; 并且在形成外延层之后，在源极和漏极区域中形成轻掺杂的源极和漏极（LDD）特征。

公开(公告)号：US20110254105A1

公开(公告)日：2011-10-20

申请号：US12761949

申请日：2010-04-16

申请人： Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

发明人： Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/28518 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.

摘要翻译： 提供了具有应变通道的半导体器件及其制造方法。 半导体器件具有形成在通道凹槽上的栅电极。 形成在栅电极的相对侧上的第一凹部和第二凹部填充有应力诱导材料。 应力诱导材料延伸到其中源极/漏极延伸部与栅电极的边缘重叠的区域中。 在一个实施例中，通道凹槽和/或第一和第二凹部的侧壁可以沿{111}面平面。

公开(公告)号：US20110193167A1

公开(公告)日：2011-08-11

申请号：US12704367

申请日：2010-02-11

申请人： Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

发明人： Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

IPC分类号： H01L27/12 ,  H01L27/105

CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate.

摘要翻译： 集成电路结构包括包括有源区的半导体衬底。 第一浅沟槽隔离（STI）区域邻接有源区域的第一侧。 MOS器件的栅电极在有源区和第一STI区之上。 MOS器件的源极/漏极应力区域包括半导体衬底中的与栅电极相邻的部分。 在半导体衬底中形成沟槽，并与有源区域的第二面相邻。 沟槽的底部不低于源极/漏极区域的底部。 层间电介质（ILD）从栅极电极延伸到沟槽内部，其中沟槽中的ILD的一部分形成第二STI区域。 第二STI区域和源极/漏极应力区域彼此分离并邻接半导体衬底的一部分。

公开(公告)号：US08633070B2

公开(公告)日：2014-01-21

申请号：US12716100

申请日：2010-03-02

申请人： Ka-Hing Fung ,  Haiting Wang ,  Han-Ting Tsai

发明人： Ka-Hing Fung ,  Haiting Wang ,  Han-Ting Tsai

IPC分类号： H01L21/84

CPC分类号： H01L29/7833 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7848

摘要： An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The method involves providing a substrate; forming a gate structure over the substrate; forming an epitaxial layer in a source and drain region of the substrate that is interposed by the gate structure; and after forming the epitaxial layer, forming a lightly doped source and drain (LDD) feature in the source and drain region.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 该方法包括提供基底; 在衬底上形成栅极结构; 在由栅极结构插入的衬底的源极和漏极区域中形成外延层; 并且在形成外延层之后，在源极和漏极区域中形成轻掺杂的源极和漏极（LDD）特征。

公开(公告)号：US08368147B2

公开(公告)日：2013-02-05

申请号：US12761949

申请日：2010-04-16

申请人： Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

发明人： Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

IPC分类号： H01L21/70

CPC分类号： H01L29/66636 ,  H01L21/28518 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.

摘要翻译： 提供了具有应变通道的半导体器件及其制造方法。 半导体器件具有形成在通道凹槽上的栅电极。 形成在栅电极的相对侧上的第一凹部和第二凹部填充有应力诱导材料。 应力诱导材料延伸到其中源极/漏极延伸部与栅电极的边缘重叠的区域中。 在一个实施例中，通道凹槽和/或第一和第二凹部的侧壁可以沿{111}面平面。

公开(公告)号：US08815722B2

公开(公告)日：2014-08-26

申请号：US13274558

申请日：2011-10-17

申请人： Ka-Hing Fung ,  Wei-Yuan Lu ,  Han-Ting Tsai

发明人： Ka-Hing Fung ,  Wei-Yuan Lu ,  Han-Ting Tsai

IPC分类号： H01L21/22 ,  H01L21/38

CPC分类号： H01L21/2257 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

摘要： A method of forming an integrated circuit includes forming a gate structure over a substrate. At least one silicon-containing layer is formed in source/drain (S/D) regions adjacent to sidewalls of the gate structure. An N-type doped silicon-containing layer is formed over the at least one silicon-containing layer. The N-type doped silicon-containing layer has an N-type dopant concentration higher than that of the at least one silicon-containing layer. The N-type doped silicon-containing layer is annealed so as to drive N-type dopants of the N-type doped silicon-containing layer to the S/D regions.

摘要翻译： 形成集成电路的方法包括在衬底上形成栅极结构。 在与栅极结构的侧壁相邻的源极/漏极（S / D）区域中形成至少一个含硅层。 在至少一个含硅层上形成N型掺杂的含硅层。 N型掺杂含硅层的N型掺杂剂浓度高于至少一种含硅层。 对N型掺杂含硅层进行退火，以将N型掺杂含硅层的N型掺杂剂驱动到S / D区。

公开(公告)号：US08053344B1

公开(公告)日：2011-11-08

申请号：US12886743

申请日：2010-09-21

申请人： Ka-Hing Fung ,  Wei-Yuan Lu ,  Han-Ting Tsai

发明人： Ka-Hing Fung ,  Wei-Yuan Lu ,  Han-Ting Tsai

IPC分类号： H01L29/00

CPC分类号： H01L21/2257 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

摘要： A method of forming an integrated circuit includes forming a gate structure over a substrate. At least one silicon-containing layer is formed in source/drain (S/D) regions adjacent to sidewalls of the gate structure. An N-type doped silicon-containing layer is formed over the at least one silicon-containing layer. The N-type doped silicon-containing layer has an N-type dopant concentration higher than that of the at least one silicon-containing layer. The N-type doped silicon-containing layer is annealed so as to drive N-type dopants of the N-type doped silicon-containing layer to the S/D regions.

摘要翻译： 形成集成电路的方法包括在衬底上形成栅极结构。 在与栅极结构的侧壁相邻的源极/漏极（S / D）区域中形成至少一个含硅层。 在至少一个含硅层上形成N型掺杂含硅层。 N型掺杂含硅层的N型掺杂剂浓度高于至少一种含硅层。 对N型掺杂含硅层进行退火，以将N型掺杂含硅层的N型掺杂剂驱动到S / D区。

公开(公告)号：US20110291201A1

公开(公告)日：2011-12-01

申请号：US12787972

申请日：2010-05-26

申请人： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

发明人： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括硅衬底。 半导体器件包括设置在衬底中的第一和第二区域。 第一和第二区域具有硅化合物材料。 半导体器件包括分别部分地设置在第一和第二区域中的第一和第二源/漏结构。 半导体器件包括设置在衬底上的第一栅极。 第一个门第一个靠近第一个地区。 半导体器件包括设置在衬底上的第二栅极。 第二个门第二个靠近第二个区域。 第二接近度不同于第一接近度。 第一源极/漏极结构和第一栅极是第一晶体管的部分，并且第二源极/漏极结构和第二栅极是第二晶体管的部分。

公开(公告)号：US08535998B2

公开(公告)日：2013-09-17

申请号：US12720075

申请日：2010-03-09

申请人： Fung Ka Hing ,  Haiting Wang ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

发明人： Fung Ka Hing ,  Haiting Wang ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

IPC分类号： H01L21/338

CPC分类号： H01L29/7833 ,  H01L21/76834 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7836

摘要： The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode.

摘要翻译： 本公开公开了一种用于制造栅极结构的示例性方法，其包括在衬底上沉积和图案化虚拟氧化物层和伪栅极电极层; 围绕所述虚拟氧化物层和所述伪栅极电极层，具有牺牲层; 用含氮介电层围绕牺牲层; 用层间介质层包围含氮介电层; 去除所述伪栅电极层; 去除虚拟氧化物层; 去除所述牺牲层以在所述含氮介电层中形成开口; 并沉积栅极电介质; 并沉积栅电极。