公开(公告)号：US20160315094A1

公开(公告)日：2016-10-27

申请号：US14850422

申请日：2015-09-10

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Megumi ISHIDUKI ,  Murato KAWAI ,  Tadashi IGUCHI ,  Yoshihiro YANAI ,  Takuya INATSUKA ,  Yoichi MINEMURA ,  Takuya MIZUTANI

IPC分类号： H01L27/115 ,  H01L23/532 ,  H01L21/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L21/027

CPC分类号： H01L27/11582 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/32139 ,  H01L22/12 ,  H01L22/20 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： A nonvolatile semiconductor memory device comprises: a memory cell region having a memory cell disposed therein; a peripheral region including a first stepped structure in which an end of a lower first layer is further from the memory cell region than is an end of an upper first layer; and a second stepped structure disposed on the first stepped structure, in which an end of a lower third layer is disposed further from the memory cell region than is an end of an upper third layer, a length in a second direction being shorter than a length in the second direction of the first layer or the second layer contacted by the second stepped structure, and a length in a third direction of the second stepped structure being shorter than a length in the third direction of the first layer or the second layer contacted by the second stepped structure.

摘要翻译： 非易失性半导体存储器件包括：存储单元区域，其中设置有存储单元; 包括第一阶梯结构的周边区域，其中下第一层的一端比上一第一层的端部更远离存储单元区域; 以及设置在所述第一阶梯结构上的第二阶梯结构，其中下部第三层的端部比所述上部第三层的端部更远离所述存储单元区域设置，第二方向上的长度短于所述第三方向的长度 在与第二阶梯结构接触的第一层或第二层的第二方向上，第二阶梯结构的第三方向上的长度比第一层或第二层的第三层的第三方向上的长度短 第二级结构。

公开(公告)号：US20150262932A1

公开(公告)日：2015-09-17

申请号：US14302976

申请日：2014-06-12

申请人： Kabushiki Kaisha Toshiba

发明人： Osamu YAMANE ,  Tadashi IGUCHI ,  Hiromitsu MASHITA

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/285 ,  H01L27/115 ,  H01L29/49

CPC分类号： H01L27/11565 ,  H01L23/5226 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/4916 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a semiconductor substrate; a multilayer interconnection structure unit; a stacked body; a channel body layer; a memory film; a contact electrode. The multilayer interconnection structure unit is provided on the semiconductor substrate, and the multilayer interconnection structure unit has interconnections. The stacked body is provided on the multilayer interconnection structure unit, and each of electrode layers and each of first insulating layers are alternately arranged in the stacked body. The channel body layer extends in the stacked body in a stacking direction of the stacked body. The memory film is provided between the channel body layer and each of the electrode layers. And the contact electrode extends in the stacked body in the stacking direction, and the contact electrode electrically connects any one of the electrode layers and any one of the interconnection layers.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括：半导体衬底; 多层互连结构单元; 堆叠的身体 通道体层; 记忆膜; 接触电极。 多层互连结构单元设置在半导体衬底上，多层互连结构单元具有互连。 层叠体设置在多层互连结构单元上，电极层和第一绝缘层中的每一个交替地布置在层叠体中。 通道体层在堆叠体的堆叠方向上延伸。 存储膜设置在通道主体层和每个电极层之间。 并且接触电极在堆叠方向上在堆叠体中延伸，并且接触电极电连接任何一个电极层和任何一个互连层。

公开(公告)号：US20170077139A1

公开(公告)日：2017-03-16

申请号：US15255786

申请日：2016-09-02

申请人： Kabushiki Kaisha Toshiba

发明人： Tadashi IGUCHI

IPC分类号： H01L27/115 ,  H01L23/50 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L27/11582 ,  H01L21/4846 ,  H01L21/4889 ,  H01L27/11575

摘要： A semiconductor memory device according to an embodiment includes a memory cell array that includes memory cells and a plurality of first conducting layers. The memory cells are arrayed in a three-dimensional manner. The first conducting layers are connected to the memory cells and are arrayed in a laminating direction. Stepped wiring portion includes a plurality of second conducting layers. The plurality of second conducting layers connect the first conducting layers and external circuits. At least one of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the first side portion side. Other ones of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the second side portion side.

摘要翻译： 根据实施例的半导体存储器件包括存储单元阵列，其包括存储单元和多个第一导电层。 存储单元以三维方式排列。 第一导电层连接到存储器单元并沿层叠方向排列。 阶梯布线部分包括多个第二导电层。 多个第二导电层连接第一导电层和外部电路。 所述多个第二导电层中的至少一个在位于所述第一侧部侧的所述阶梯布线部的顶面上具有接触形成区域。 多个第二导电层中的其它导电层包括在位于第二侧部侧的阶梯布线部分的顶表面上的接触形成区域。

公开(公告)号：US20150060976A1

公开(公告)日：2015-03-05

申请号：US14194779

申请日：2014-03-02

申请人： Kabushiki Kaisha Toshiba

发明人： Tadashi IGUCHI

IPC分类号： H01L27/115

CPC分类号： H01L27/11556 ,  H01L29/66833 ,  H01L29/7926

摘要： According to an embodiment, a solid state storage device includes a first gate; a plurality of conductive layers having insulating layers therebetween, one of the insulating layers located on the first gate, an interconnection region extending inwardly of the first gate, a first semiconductor layer extending through the plurality of conductive layers and insulating layers, a second semiconductor layer extending through the plurality of conductive layers and insulating layers; a third semiconductor layer extending through the interconnection region and electrically connecting the first and second semiconductor layers, and an insulator extending through the plurality of conductive layers and insulating layers at a location intermediate of the first and second semiconductor layers, and also extending inwardly of the interconnection region.

摘要翻译： 根据实施例，固态存储装置包括第一门; 多个导电层，其间具有绝缘层，位于第一栅极上的绝缘层之一，从第一栅极向内延伸的互连区域，延伸穿过多个导电层和绝缘层的第一半导体层，第二半导体层 延伸穿过多个导电层和绝缘层; 延伸穿过所述互连区域并电连接所述第一和第二半导体层的第三半导体层，以及在所述第一和第二半导体层的中间位置处延伸穿过所述多个导电层和绝缘层的绝缘体， 互连区域。

公开(公告)号：US20170077107A1

公开(公告)日：2017-03-16

申请号：US15069158

申请日：2016-03-14

申请人： Kabushiki Kaisha Toshiba

发明人： Tadashi IGUCHI

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L29/423

CPC分类号： H01L27/11575 ,  H01L27/11573 ,  H01L27/11582

摘要： A method for manufacturing includes forming a first insulating film on a substrate, forming first to third portions in the first insulating film, forming a second insulating film on the first insulating film, removing a part of the second portion, a portion including a region directly above the part of the second portion of the second insulating film, and at least a part of a portion including a region directly above the other part of the second portion of the second insulating film, and forming a first stacked body, forming a stacked film by alternately stacking third and fourth insulating films, and forming a stacked structure by processing a remaining part of the stacked film into a stepped pattern forming steps at each of the third insulating films. A depression is formed on the region directly above the third portion in an upper surface of the second insulating film.

摘要翻译： 一种制造方法包括在基板上形成第一绝缘膜，在第一绝缘膜中形成第一至第三部分，在第一绝缘膜上形成第二绝缘膜，除去第二部分的一部分，直接包括区域的部分 在第二绝缘膜的第二部分的一部分上方，以及包含直接在第二绝缘膜的第二部分的另一部分上方的区域的部分的至少一部分，并形成第一层叠体，形成层叠膜 通过交替堆叠第三绝缘膜和第四绝缘膜，并且通过将堆叠膜的剩余部分加工成在每个第三绝缘膜上形成台阶的阶梯状图案来形成堆叠结构。 在第二绝缘膜的上表面的第三部分正上方的区域上形成凹陷。

公开(公告)号：US20160268298A1

公开(公告)日：2016-09-15

申请号：US14849743

申请日：2015-09-10

申请人： Kabushiki Kaisha Toshiba

发明人： Tadashi IGUCHI ,  Murato Kawai ,  Toru Matsuda ,  Hisashi Kato ,  Megumi Ishiduki

IPC分类号： H01L27/115 ,  H01L23/522 ,  H01L21/311 ,  G11C16/04 ,  H01L21/02

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L23/5226 ,  H01L27/11565 ,  H01L27/11575

摘要： A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.

摘要翻译： 根据实施例的半导体存储器件包括存储单元阵列，其被配置为具有通过串联连接第一选择晶体管，存储晶体管和第二选择晶体管而获得的存储器串。 当彼此交叉的三个方向分别设置为第一，第二和第三方向时，存储单元阵列具有作为第一选择晶体管的控制栅极的第一导电层，作为存储晶体管的控制栅极的第二导电层，以及 第三导电层作为第二选择晶体管的控制栅极，其在第三方向上层叠。 第一导电层的端部和第三导电层的端部形成为在第一方向上延伸的台阶形状，并且第二导电层的端部形成为在第一方向和第二方向的两个方向上延伸的台阶形状。

公开(公告)号：US20160079266A1

公开(公告)日：2016-03-17

申请号：US14657417

申请日：2015-03-13

申请人： Kabushiki Kaisha Toshiba

发明人： Nozomi KIDO ,  Masao IWASE ,  Tadashi IGUCHI

IPC分类号： H01L27/115 ,  H01L23/528

CPC分类号： H01L27/11582 ,  H01L27/1157

摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a selection gate electrode, a semiconductor pillar, a first insulating member, a second insulating member, a third insulating member. The stacked body is provided on the substrate. The selection gate electrode is provided on the stacked body. The first insulating member divides the stacked body in a first direction. The second insulating member is provided in an area directly above the first insulating member and dividing the selection gate electrode in the first direction. The third insulating member is provided in a region other than the area directly above the first insulating member and dividing the selection gate electrode in the first direction. An average width of the second insulating member in the first direction is larger than an average width of the third insulating member in the first direction.

摘要翻译： 根据一个实施例，半导体存储器件包括层叠体，选择栅电极，半导体柱，第一绝缘构件，第二绝缘构件，第三绝缘构件。 层叠体设置在基板上。 选择栅电极设置在层叠体上。 第一绝缘构件沿着第一方向分隔堆叠体。 第二绝缘构件设置在第一绝缘构件正上方的区域中，并且沿第一方向分割选择栅电极。 第三绝缘构件设置在除了第一绝缘构件正上方的区域以外的区域中，并且在第一方向上划分选择栅电极。 所述第二绝缘构件在所述第一方向上的平均宽度大于所述第三绝缘构件在所述第一方向上的平均宽度。

公开(公告)号：US20140027836A1

公开(公告)日：2014-01-30

申请号：US14042030

申请日：2013-09-30

申请人： Kabushiki Kaisha Toshiba

发明人： Tadashi IGUCHI ,  Ryota KATSUMATA

IPC分类号： H01L23/48 ,  H01L27/115

CPC分类号： H01L23/481 ,  H01L21/28282 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: first and second stacked bodies, first and second semiconductor pillars, a connection portion, a memory film, and a partitioning insulating layer. The stacked bodes include electrode films stacked along a first axis and an inter-electrode insulating film provided between the electrode films. Through-holes are provided in the stacked bodies. The semiconductor pillars are filled into the through-holes. The connection portion electrically connects the semiconductor pillars. The memory film is provided between the semiconductor pillars and the electrode films. The partitioning insulating layer partitions the first and second electrode films. A side surface of the first through-hole on the partitioning insulating layer side and a side surface of the second through-hole on the partitioning insulating layer side have a portion parallel to a plane orthogonal to a second axis from the first stacked body to the second stacked body.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括：第一和第二堆叠体，第一和第二半导体柱，连接部分，存储膜和分隔绝缘层。 堆叠的栅极包括沿着第一轴线堆叠的电极膜和设置在电极膜之间的电极间绝缘膜。 在堆叠体中设置有通孔。 半导体柱被填充到通孔中。 连接部电连接半导体支柱。 存储膜设置在半导体柱和电极膜之间。 分隔绝缘层分隔第一和第二电极膜。 分隔绝缘层侧的第一通孔的侧面和分隔绝缘层侧的第二贯通孔的侧面具有与从第一层叠体到第二贯通孔的第二轴正交的平面的部分 第二堆叠体。